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From:   Stephen Boyd <swboyd@chromium.org>
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Date:   Tue, 8 Feb 2022 13:08:19 -0800
Message-ID: <CAE-0n50PAtGfvHXjNrvQYe6edNEfJvEc1uYZFUeW2KHxn6fsBA@mail.gmail.com>
Subject: Re: [PATCH v2 1/3] arm64: dts: qcom: sc7280: Add pinmux for I2S
 speaker and Headset
To:     Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>,
        agross@kernel.org, bjorn.andersson@linaro.org,
        devicetree@vger.kernel.org, dianders@chromium.org,
        judyhsiao@chromium.org, linux-arm-msm@vger.kernel.org,
        linux-kernel@vger.kernel.org, robh+dt@kernel.org,
        rohitkr@codeaurora.org, srinivas.kandagatla@linaro.org
Cc:     Venkata Prasad Potturu <quic_potturu@quicinc.com>
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Precedence: bulk

Quoting Srinivasa Rao Mandadapu (2022-02-08 07:34:12)
> Add AMP enable node and pinmux for primary and secondary I2S
> for SC7280 based platforms.
>
> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 40 ++++++++++++++++++++++++++++++++
>  arch/arm64/boot/dts/qcom/sc7280.dtsi     | 40 ++++++++++++++++++++++++++++++++
>  2 files changed, 80 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> index d623d71..c7d6c46 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> @@ -436,6 +436,39 @@
>                 qcom,drive-strength = <3>;
>         };
>  };

Newline here

> +&pri_mi2s_data0 {
> +       drive-strength = <6>;
> +};
> +
> +&pri_mi2s_data1 {
> +       drive-strength = <6>;
> +};
> +
> +&pri_mi2s_mclk {
> +       drive-strength = <6>;
> +};
> +
> +&pri_mi2s_sclk {
> +       drive-strength = <6>;
> +};
> +
> +&pri_mi2s_ws {
> +       drive-strength = <6>;
> +};
> +
> +&sec_mi2s_data0 {
> +       drive-strength = <6>;
> +       bias-disable;
> +};
> +
> +&sec_mi2s_sclk {
> +       drive-strength = <6>;
> +       bias-disable;
> +};
> +
> +&sec_mi2s_ws {
> +       drive-strength = <6>;
> +};

Please sort these nodes alphabetically on node name.

>
>  &qspi_cs0 {
>         bias-disable;
> @@ -491,6 +524,13 @@
>  };
>
>  &tlmm {
> +       amp_en: amp-en {
> +               pins = "gpio63";
> +               function = "gpio";
> +               bias-disable;

Is there an external pull?

> +               drive-strength = <2>;
> +       };
> +
>         nvme_pwren: nvme-pwren {
>                 function = "gpio";
>         };
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 937c2e0..76e73e9 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -3461,6 +3461,46 @@
>                                 };
>                         };
>
> +                       pri_mi2s_data0: pri-mi2s-data0 {
> +                               pins = "gpio98";
> +                               function = "mi2s0_data0";
> +                       };
> +
> +                       pri_mi2s_data1: pri-mi2s-data1 {
> +                               pins = "gpio99";
> +                               function = "mi2s0_data1";
> +                       };
> +
> +                       pri_mi2s_mclk: pri-mi2s-mclk {
> +                               pins = "gpio96";
> +                               function = "pri_mi2s";
> +                       };
> +
> +                       pri_mi2s_sclk: pri-mi2s-sclk {
> +                               pins = "gpio97";
> +                               function = "mi2s0_sck";
> +                       };
> +
> +                       pri_mi2s_ws: pri-mi2s-ws {
> +                               pins = "gpio100";
> +                               function = "mi2s0_ws";
> +                       };
> +
> +                       sec_mi2s_data0: sec-mi2s-data0 {
> +                               pins = "gpio107";
> +                               function = "mi2s1_data0";
> +                       };
> +
> +                       sec_mi2s_sclk: sec-mi2s-sclk {
> +                               pins = "gpio106";
> +                               function = "mi2s1_sck";
> +                       };
> +
> +                       sec_mi2s_ws: sec-mi2s-ws {
> +                               pins = "gpio108";
> +                               function = "mi2s1_ws";
> +                       };

Please sort these nodes alphabetically on node name.