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From:   Bharat Kumar Gogada <bharatku@xilinx.com>
To:     Bjorn Helgaas <helgaas@kernel.org>
CC:     "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
        "bhelgaas@google.com" <bhelgaas@google.com>,
        Michal Simek <michals@xilinx.com>
Subject: RE: [PATCH 1/2] PCI: xilinx-cpm: Update YAML schemas for Versal CPM5
 Root Port
Thread-Topic: [PATCH 1/2] PCI: xilinx-cpm: Update YAML schemas for Versal CPM5
 Root Port
Thread-Index: AQHYG9kAFKEhuJg1KE+3u5Sm8qGShKyIaTQAgAEOzVA=
Date:   Tue, 8 Feb 2022 10:38:07 +0000
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References: <20220207041250.1658-2-bharat.kumar.gogada@xilinx.com>
 <20220207182806.GA408432@bhelgaas>
In-Reply-To: <20220207182806.GA408432@bhelgaas>
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> Subject: Re: [PATCH 1/2] PCI: xilinx-cpm: Update YAML schemas for Versal
> CPM5 Root Port
>=20
> It looks like the subject line convention here would be something
> like:
>=20
>   dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
>=20
> (From "git log --oneline Documentation/devicetree/bindings/pci/")
>=20
> On Mon, Feb 07, 2022 at 09:42:48AM +0530, Bharat Kumar Gogada wrote:
> > Xilinx Versal Premium series has CPM5 block which supports Root port
> > functioning at Gen5 speed.
> > Add support for YAML schemas documentation for Versal CPM5 Root Port
> driver.
>=20
> s/Root port/Root Port/ to be consistent.
> Add blank line between paragraphs.
>=20
Thanks Bjorn, will do the changes in next patch.

Regards,
Bharat