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From:   Bharat Kumar Gogada <bharatku@xilinx.com>
To:     Bjorn Helgaas <helgaas@kernel.org>
CC:     "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
        "bhelgaas@google.com" <bhelgaas@google.com>,
        Michal Simek <michals@xilinx.com>
Subject: RE: [PATCH 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root
 Port driver
Thread-Topic: [PATCH 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root
 Port driver
Thread-Index: AQHYG9kFP8Vxuz1vvUqhZX2L0Vr9iayIafIAgAEOR6A=
Date:   Tue, 8 Feb 2022 10:38:20 +0000
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References: <20220207041250.1658-4-bharat.kumar.gogada@xilinx.com>
 <20220207183046.GA408682@bhelgaas>
In-Reply-To: <20220207183046.GA408682@bhelgaas>
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> Subject: Re: [PATCH 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Roo=
t
> Port driver
>=20
> In subject, possibly:
>=20
>   PCI: xilinx-cpm: Add Versal CPM5 Root Port support
>=20
> since you're adding support for a *device*, not for a *driver*.
>=20
> On Mon, Feb 07, 2022 at 09:42:50AM +0530, Bharat Kumar Gogada wrote:
> > Xilinx Versal Premium series has CPM5 block which supports Root port
> > functioning at Gen5 speed.
> > Xilinx Versal CPM5 has few changes with existing CPM block.
> > - CPM5 has dedicated register space for control and status registers.
> > - CPM5 legacy interrupt handling needs additional register bit
> >   to enable and handle legacy interrupts.
>=20
> s/Root port/Root Port/ to be consistent.
> Add blank line between paragraphs.
>=20
Thanks Bjorn, will do the changes in next patch.

Regards,
Bharat