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Date:   Wed, 9 Feb 2022 08:04:10 +0100
From:   Jean Delvare <jdelvare@suse.de>
To:     Terry Bowman <Terry.Bowman@amd.com>
Cc:     linux@roeck-us.net, linux-watchdog@vger.kernel.org,
        linux-i2c@vger.kernel.org, wsa@kernel.org,
        andy.shevchenko@gmail.com, rafael.j.wysocki@intel.com,
        linux-kernel@vger.kernel.org, wim@linux-watchdog.org,
        rrichter@amd.com, thomas.lendacky@amd.com, sudheesh.mavila@amd.com,
        Nehal-bakulchandra.Shah@amd.com, Basavaraj.Natikar@amd.com,
        Shyam-sundar.S-k@amd.com, Mario.Limonciello@amd.com
Subject: Re: [PATCH v4 0/9] i2c: piix4: Replace cd6h/cd7h port I/O accesses
 with MMIO accesses
Message-ID: <20220209080410.1e7dddd9@endymion.delvare>
In-Reply-To: <27e60021-30cb-3b1c-f429-2618bf891e5e@amd.com>
References: <20220130184130.176646-1-terry.bowman@amd.com>
        <20220208181114.180a99ba@endymion.delvare>
        <4ae57999-0f23-7578-008d-2009bc36d46b@amd.com>
        <20220208224653.6a62ba22@endymion.delvare>
        <27e60021-30cb-3b1c-f429-2618bf891e5e@amd.com>
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On Tue, 8 Feb 2022 17:03:09 -0600, Terry Bowman wrote:
> On 2/8/22 15:46, Jean Delvare wrote:
> > If so, while there's indeed nothing to be done for the most recent
> > systems where only MMIO access is possible, you may still need to
> > enable MMIO access through legacy I/O if you try to use MMIO on
> > chipsets where both are possible. I'm not sure what exactly where you
> > set the limit. In the last patch you say that 0x51 is the first
> > revision of the family 17h CPUs, but is family 17h the first where MMIO
> > is available, or the first where legacy I/O isn't?
>
> Family 17h, SMBus PCI ID >= 0x51 is the first where cd6h/cd7h port I/O is disabled. 
> If SMBus PCI ID < 0x51 then cd6h/cd7h port I/O is used. 

OK, we are safe then :-)

-- 
Jean Delvare
SUSE L3 Support