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From:   Arnd Bergmann <arnd@arndb.de>
Date:   Wed, 9 Feb 2022 10:39:39 +0100
Message-ID: <CAK8P3a1swyDBvSTg9a6tUnd2V2Zi=ANpJWhJpWwfvp7ArZpwVg@mail.gmail.com>
Subject: Re: [PATCH v3] ARM: dts: add DT for lan966x SoC and 2-port board pcb8291
To:     Kavyasree.Kotagiri@microchip.com
Cc:     Arnd Bergmann <arnd@arndb.de>,
        Nicolas Ferre <Nicolas.Ferre@microchip.com>,
        Olof Johansson <olof@lixom.net>, SoC Team <soc@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        DTML <devicetree@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
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On Wed, Feb 9, 2022 at 10:02 AM <Kavyasree.Kotagiri@microchip.com> wrote:
> > > On 13/01/2022 at 09:00, Kavyasree Kotagiri wrote:

> > > > +&gpio {
> > > > +     fc_shrd7_pins: fc_shrd7-pins {
> > > > +             pins = "GPIO_49";
> > > > +             function = "fc_shrd7";
> > > > +     };
> >
> > These properties don't look like most pinctrl nodes, has the binding
> > been reviewed?
> > I don't see it in Documentation/devicetree/bindings/pinctrl/
> >
> This is similar to the ones used in Microchip Ocelot and Sparx5 pinctrl.
> For example, see usart_pins of gpio nodes in below links:
> https://sbexr.rabexc.org/latest/sources//84/d39b543790ff25.jhtml
> https://searchcode.com/file/333750634/arch/mips/boot/dts/mscc/ocelot.dtsi/

Ok, I see, so this was reviewed by both Rob and LinusW, I assume it's fine
then, though the use of strings with capital letters, with all pins
named "GPIO_*"
still looks odd.

For my understanding, would you describe the lan966x family as
a follow-up to Ocelot, with the CPU cores replaced and flexcom added,
or should I think of it as a SAMA7 based SoC design that incorporates
the Vitesse switch IP?

        Arnd