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Ruhl" To: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, bhelgaas@google.com, logang@deltatee.com, michael.j.ruhl@intel.com Cc: dan.j.williams@intel.com Subject: [PATCH] PCI/P2PDMA: Update device table with 3rd gen Xeon platform information Date: Wed, 9 Feb 2022 11:28:01 -0500 Message-Id: <20220209162801.7647-1-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to do P2P communication the bridge ID of the platform must be in the P2P device table. Update the P2P device table with a device id for the 3rd Gen Intel Xeon Scalable Processors. Reviewed-by: Dan Williams Signed-off-by: Michael J. Ruhl --- drivers/pci/p2pdma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c index 1015274bd2fe..30b1df3c9d2f 100644 --- a/drivers/pci/p2pdma.c +++ b/drivers/pci/p2pdma.c @@ -321,6 +321,7 @@ static const struct pci_p2pdma_whitelist_entry { {PCI_VENDOR_ID_INTEL, 0x2032, 0}, {PCI_VENDOR_ID_INTEL, 0x2033, 0}, {PCI_VENDOR_ID_INTEL, 0x2020, 0}, + {PCI_VENDOR_ID_INTEL, 0x09a2, 0}, {} }; -- 2.31.1