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From:   Tim Harvey <tharvey@gateworks.com>
Date:   Wed, 9 Feb 2022 08:31:23 -0800
Message-ID: <CAJ+vNU3EY0qp-6oQ6Bjd4mZCKv9AeqiaJp=FSrN84P=8atKLrw@mail.gmail.com>
Subject: Re: [PATCH net v3] net: phy: intel-xway: enable integrated led functions
To:     Andrew Lunn <andrew@lunn.ch>
Cc:     Martin Schiller <ms@dev.tdt.de>, Hauke Mehrtens <hauke@hauke-m.de>,
        martin.blumenstingl@googlemail.com,
        Florian Fainelli <f.fainelli@gmail.com>, hkallweit1@gmail.com,
        Russell King - ARM Linux <linux@armlinux.org.uk>,
        David Miller <davem@davemloft.net>, kuba@kernel.org,
        netdev <netdev@vger.kernel.org>,
        open list <linux-kernel@vger.kernel.org>
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On Fri, Feb 4, 2022 at 2:54 PM Andrew Lunn <andrew@lunn.ch> wrote:
>
> > The PHY_INTERRFACE_MODE_NA is a neat trick that I will remember but it
> > would only help with the rgmii delay issue and not the LED issue (this
> > patch). The GPY111 has some really nasty errata that is going to cause
> > me to have a very hackish work-around anyway and I will be disabling
> > the PHY driver to stay out of the way of that workaround
>
> Well, ideally we want the workaround for the erratas in the kernel
> drivers. In the long run, you will get less surprises if you add what
> you need to Linux, not hide stuff away in the bootloader.

Andrew,

I agree it is best to get workarounds for errata in the kernel where
possible but this one is going to be a mess. There are 3 errata for
this part and 2 of them require a toggle of the reset pin as a work
around. Even if the mii bus can export a function for the phy to call
to toggle reset in my case one of my boards has 2 of these PHY's (1 on
a RGMII MAC and 1 on a SGMII MAC) on different MDIO busses that share
a reset pin so if I trigger a reset I have to re-configure the other
phy as well.

The errata can be summarized as:
- 1 out of 100 boots or cable plug events RGMII GbE link will end up
going down and up 3 to 4 times then resort to a 100m link; workaround
has been found to require a pin level reset
- 1 out of 100 boots or cable plug events (varies per board) SGMII
will fail link between the MAC and PHY; workaround has been found to
require a pin level reset
- occasionally the phy will come up with a high bit error rate between
the MAC and PHY; workaround has been found to require a soft reset or
ANEG restart

>
> > As far as changing a driver to force a LED configuration with no dt
> > binding input (like this patch does) it feels wrong for exactly the
> > same reason - LED configuration for this PHY can be done via
> > pin-strapping and this driver now undoes that with this patch.
>
> Is it possible to read the pin strapping pins? If we know it has been
> pin strapped, then a patch to detect this and not change the LED
> configuration seems very likely to be accepted.
>

No, you can read the current LED configuration but you don't know if
it was set via strapping or boot firmware.

Best regards,

Tim