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[213.179.129.39]) by smtp.gmail.com with ESMTPSA id b7sm9215079edv.58.2022.02.09.23.02.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Feb 2022 23:02:13 -0800 (PST) Date: Thu, 10 Feb 2022 08:02:12 +0100 From: Jiri Pirko To: Jakub Kicinski Cc: Moshe Shemesh , "David S. Miller" , Jiri Pirko , Saeed Mahameed , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next 0/4] net/mlx5: Introduce devlink param to disable SF aux dev probe Message-ID: References: <1644340446-125084-1-git-send-email-moshe@nvidia.com> <20220208212341.513e04bf@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com> <20220209172525.19977e8c@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220209172525.19977e8c@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thu, Feb 10, 2022 at 02:25:25AM CET, kuba@kernel.org wrote: >On Wed, 9 Feb 2022 09:39:54 +0200 Moshe Shemesh wrote: >> Well we don't have the SFs at that stage, how can we tell which SF will >> use vnet and which SF will use eth ? > >On Wed, 9 Feb 2022 10:57:21 +0100 Jiri Pirko wrote: >> It's a different user. One works with the eswitch and creates the port >> function. The other one takes the created instance and works with it. >> Note that it may be on a different host. > >It is a little confusing, so I may well be misunderstanding but the >cover letter says: > >$ devlink dev param set pci/0000:08:00.0 name enable_sfs_aux_devs \ > value false cmode runtime > >$ devlink port add pci/0000:08:00.0 flavour pcisf pfnum 0 sfnum 11 > >So both of these run on the same side, no? > >What I meant is make the former part of the latter: > >$ devlink port add pci/0000:08:00.0 flavour pcisf pfnum 0 sfnum 11 noprobe I see. So it would not be "global policy" but per-instance option during creation. That makes sense. I wonder if the HW is capable of such flow, Moshe, Saeed? > > >Maybe worth clarifying - pci/0000:08:00.0 is the eswitch side and >auxiliary/mlx5_core.sf.1 is the... "customer" side, correct? Yep.