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From:   <Kavyasree.Kotagiri@microchip.com>
To:     <michael@walle.cc>
CC:     <Manohar.Puri@microchip.com>, <UNGLinuxDriver@microchip.com>,
        <alexandre.belloni@bootlin.com>, <arnd@arndb.de>,
        <devicetree@vger.kernel.org>,
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        <linux-kernel@vger.kernel.org>, <Nicolas.Ferre@microchip.com>,
        <olof@lixom.net>, <robh+dt@kernel.org>, <soc@kernel.org>
Subject: RE: [PATCH v4] ARM: dts: add DT for lan966 SoC and 2-port board
 pcb8291
Thread-Topic: [PATCH v4] ARM: dts: add DT for lan966 SoC and 2-port board
 pcb8291
Thread-Index: AQHYHaYU1qtS5sG/10aA2sqGSWL+96yLj0MAgAD4oLA=
Date:   Thu, 10 Feb 2022 09:40:05 +0000
Message-ID: <CO1PR11MB486534A2987684CC7402CE06922F9@CO1PR11MB4865.namprd11.prod.outlook.com>
References: <20220209111318.21112-1-kavyasree.kotagiri@microchip.com>
 <20220209184600.1230365-1-michael@walle.cc>
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> EXTERNAL EMAIL: Do not click links or open attachments unless you know th=
e
> content is safe
>=20
> Hi,
>=20
> > +     clocks {
> [..]
> > +
> > +             nic_clk: nic_clk {
>=20
> What does nic_clk stand for? If I had to guess, it
> has something to do with network. But..
>=20
NIC clock is the clock used by AXI, AHB fabric and APB bridges which connec=
ts all the peripherals.
It is named so because the AXI fabric is based on NIC400 IP from ARM

> > +                     compatible =3D "fixed-clock";
> > +                     #clock-cells =3D <0>;
> > +                     clock-frequency =3D <200000000>;
> > +             };
> > +     };
> > +
> > +     clks: clock-controller@e00c00a8 {
> > +             compatible =3D "microchip,lan966x-gck";
> > +             #clock-cells =3D <1>;
> > +             clocks =3D <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
> > +             clock-names =3D "cpu", "ddr", "sys";
> > +             reg =3D <0xe00c00a8 0x38>;
> > +     };
> > +
> > +     timer {
> > +             compatible =3D "arm,armv7-timer";
> > +             interrupt-parent =3D <&gic>;
> > +             interrupts =3D <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +                          <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +                          <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +                          <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
> IRQ_TYPE_LEVEL_LOW)>;
> > +             clock-frequency =3D <37500000>;
> > +             arm,cpu-registers-not-fw-configured;
> > +     };
> > +
> > +     soc {
> > +             compatible =3D "simple-bus";
> > +             #address-cells =3D <1>;
> > +             #size-cells =3D <1>;
> > +             ranges;
> > +
> > +             flx0: flexcom@e0040000 {
> > +                     compatible =3D "atmel,sama5d2-flexcom";
> > +                     reg =3D <0xe0040000 0x100>;
> > +                     clocks =3D <&clks GCK_ID_FLEXCOM0>;
> > +                     #address-cells =3D <1>;
> > +                     #size-cells =3D <1>;
> > +                     ranges =3D <0x0 0xe0040000 0x800>;
> > +                     status =3D "disabled";
> > +             };
> > +
> > +             flx1: flexcom@e0044000 {
> > +                     compatible =3D "atmel,sama5d2-flexcom";
> > +                     reg =3D <0xe0044000 0x100>;
> > +                     clocks =3D <&clks GCK_ID_FLEXCOM1>;
> > +                     #address-cells =3D <1>;
> > +                     #size-cells =3D <1>;
> > +                     ranges =3D <0x0 0xe0044000 0x800>;
> > +                     status =3D "disabled";
> > +             };
> > +
> > +             trng: trng@e0048000 {
> > +                     compatible =3D "atmel,at91sam9g45-trng";
> > +                     reg =3D <0xe0048000 0x100>;
> > +                     clocks =3D <&nic_clk>;
>=20
> .. it is used here..
>=20
>=20
> > +             };
> > +
> > +             aes: aes@e004c000 {
> > +                     compatible =3D "atmel,at91sam9g46-aes";
> > +                     reg =3D <0xe004c000 0x100>;
> > +                     interrupts =3D <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> > +                     dmas =3D <&dma0 AT91_XDMAC_DT_PERID(13)>,
> > +                            <&dma0 AT91_XDMAC_DT_PERID(12)>;
> > +                     dma-names =3D "rx", "tx";
> > +                     clocks =3D <&nic_clk>;
>=20
> .. and here. and so on.
>=20
> So, is it some kind of internal clock?
>=20
> > +                     interrupts =3D <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> > +             };
> > +
> > +             watchdog: watchdog@e0090000 {
> > +                     compatible =3D "snps,dw-wdt";
> > +                     reg =3D <0xe0090000 0x1000>;
> > +                     interrupts =3D <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> > +                     clocks =3D <&nic_clk>;
>=20
> Btw. can we disable all nodes by default and enable them
> in the board dts files?
I would like to have only board specific nodes enabled in dts files and res=
t of them in dtsi file

Thanks,
Kavya