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[212.85.90.115]) by smtp.gmail.com with ESMTPSA id f5sm1362483lfs.245.2022.02.13.07.32.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Feb 2022 07:32:53 -0800 (PST) From: Tobias Waldekranz To: "Russell King (Oracle)" Cc: davem@davemloft.net, kuba@kernel.org, netdev@vger.kernel.org, Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , Marek =?utf-8?Q?Beh=C3=BAn?= , linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next] net: dsa: mv88e6xxx: Fix validation of built-in PHYs on 6095/6097 In-Reply-To: References: <20220213003702.2440875-1-tobias@waldekranz.com> Date: Sun, 13 Feb 2022 16:32:51 +0100 Message-ID: <87tud2aijg.fsf@waldekranz.com> MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Feb 13, 2022 at 12:58, "Russell King (Oracle)" wrote: > Hi, > > Thanks for spotting this. Some comments below. > > On Sun, Feb 13, 2022 at 01:37:01AM +0100, Tobias Waldekranz wrote: >> +static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, >> + struct phylink_config *config) >> +{ >> + u8 cmode = chip->ports[port].cmode; >> + >> + config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; >> + >> + if (mv88e6xxx_phy_is_internal(chip->ds, port)) { >> + if (cmode == MV88E6185_PORT_STS_CMODE_PHY) >> + __set_bit(PHY_INTERFACE_MODE_MII, >> + config->supported_interfaces); > > Hmm. First, note that with mv88e6xxx_get_caps(), you'll end up with both > MII and GMII here. GMII is necessary as that's the phylib default if no I did notice that. > one specifies anything different in the firmware description. I assume > you've noticed a problem because you specify MII for the internal ports > in firmware? Precisely. > I'm wondering what the point of checking the cmode here is - if the port > is internal, won't this switch always have cmode == PHY? For all intents and purposes: I think so. It is just that the functional spec. also lists cmode == 4 == disabled (PHYDetect == 0) for the internal ports. So I figured that there might be some way of strapping ports as disabled that I had never come across. Do you think we should drop it?