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[71.197.186.152]) by smtp.gmail.com with ESMTPSA id f3sm28492008pfe.43.2022.02.11.12.54.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Feb 2022 12:54:06 -0800 (PST) From: Kevin Hilman To: Christian Hewitt Cc: Rob Herring , Mark Rutland , Neil Armstrong , devicetree , linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: dts: meson: remove CPU opps below 1GHz for G12B/SM1 In-Reply-To: References: <20220209135535.29547-1-christianshewitt@gmail.com> <7h7da3o6cg.fsf@baylibre.com> Date: Fri, 11 Feb 2022 12:54:06 -0800 Message-ID: <7ha6exm8ep.fsf@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Christian Hewitt writes: >> On 10 Feb 2022, at 5:31 am, Kevin Hilman wrote: >>=20 >> Christian Hewitt writes: >>=20 >>> Amlogic G12B and SM1 devices experience CPU stalls and random board >>> wedges when the system idles and CPU cores clock down to lower opp >>> points. Recent vendor kernels include a change to remove 100-250MHz >>> (with no explanation) [0] but other downstream sources also remove >>> the 500/667MHz points (also with no explanation). Unless 100-667Mhz >>> opps are removed or the CPU governor forced to performance, stalls >>> are observed, so let's remove them an improve stability/uptime. >>=20 >> Just curious: what CPUfreq governor do you use by default for the >> LibreELEC kernel? > > LE uses ondemand. One of the original clues on the problem us that the > issue isn=E2=80=99t seen in some of the retro-gaming forks on LE's codeba= se > which use the performance governor (and overclocks, etc.) OK, thanks. And does LE ever do full system suspend/resume? Are things stable for you across multiple suspend/resume cycles on G12B or SM1 devices? I'm seeing hat with either powersave or performance, repeated suspend/resume is stable, but with ondemand or schedultil it's not, even with $SUBJECT patch applied. If you have some time to test, seeing how long this loop[1] runs with ondemand vs performance or powersave would be instructive. Even more interesting... if I set the governor to performance, but set the suspend OPP to 1GHz[2] (which is what it would be for the powersave governor), it is also unstable. This suggests (to me) that any sort of OPP change during the suspend/resume process is going to be unstable. Now the challenge is to understand why so we can avoid it. Thanks, Kevin [1] while true; do echo "=3D=3D=3D SUSPEND =3D=3D=3D" cat /sys/devices/system/cpu/cpufreq/policy0/scaling_governor cat /sys/devices/system/cpu/cpufreq/policy0/scaling_cur_freq cat /sys/devices/system/cpu/cpufreq/policy2/scaling_governor cat /sys/devices/system/cpu/cpufreq/policy2/scaling_cur_freq echo rtcwake -d rtc0 -m mem -s4 echo "=3D=3D=3D RESUME =3D=3D=3D" sleep 4 done [2] diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi b/arch/arm64= /boot/dts/amlogic/meson-g12b-s922x.dtsi index 1e5d0ee5d541..37da8be85288 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi @@ -14,6 +14,7 @@ cpu_opp_table_0: opp-table-0 { opp-100000000 { opp-hz =3D /bits/ 64 <100000000>; opp-microvolt =3D <731000>; + opp-suspend; }; =20 opp-250000000 { @@ -79,6 +80,7 @@ cpub_opp_table_1: opp-table-1 { opp-100000000 { opp-hz =3D /bits/ 64 <100000000>; opp-microvolt =3D <751000>; + opp-suspend; }; =20 opp-250000000 {