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[23.128.96.19]) by mx.google.com with ESMTPS id q20si624792pgt.802.2022.02.14.11.55.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Feb 2022 11:55:36 -0800 (PST) Received-SPF: softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) client-ip=23.128.96.19; Authentication-Results: mx.google.com; spf=softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7B88DD5DD8; Mon, 14 Feb 2022 11:37:19 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236428AbiBMORR (ORCPT + 99 others); Sun, 13 Feb 2022 09:17:17 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:37922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236433AbiBMORG (ORCPT ); Sun, 13 Feb 2022 09:17:06 -0500 Received: from 189.cn (ptr.189.cn [183.61.185.101]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0139B5F267; Sun, 13 Feb 2022 06:16:59 -0800 (PST) HMM_SOURCE_IP: 10.64.8.41:34274.536114013 HMM_ATTACHE_NUM: 0000 HMM_SOURCE_TYPE: SMTP Received: from clientip-114.242.206.180 (unknown [10.64.8.41]) by 189.cn (HERMES) with SMTP id 47B09100248; Sun, 13 Feb 2022 22:16:57 +0800 (CST) Received: from ([114.242.206.180]) by gateway-151646-dep-b7fbf7d79-9vctg with ESMTP id 84b9622b98e3492ca64a02f2f5fd1ef5 for mripard@kernel.org; Sun, 13 Feb 2022 22:16:59 CST X-Transaction-ID: 84b9622b98e3492ca64a02f2f5fd1ef5 X-Real-From: 15330273260@189.cn X-Receive-IP: 114.242.206.180 X-MEDUSA-Status: 0 Sender: 15330273260@189.cn From: Sui Jingfeng <15330273260@189.cn> To: Maxime Ripard , Thomas Zimmermann , Roland Scheidegger , Zack Rusin , Christian Gmeiner , David Airlie , Daniel Vetter , Rob Herring , Thomas Bogendoerfer , Dan Carpenter , Krzysztof Kozlowski , Andrey Zhizhikin , Sam Ravnborg , "David S . Miller" , Jiaxun Yang , Lucas Stach , Maarten Lankhorst , Ilia Mirkin , Qing Zhang , Li Yi , suijingfeng Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH v7 3/7] MIPS: Loongson: introduce dts for ls3A4000 evaluation board Date: Sun, 13 Feb 2022 22:16:45 +0800 Message-Id: <20220213141649.1115987-4-15330273260@189.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220213141649.1115987-1-15330273260@189.cn> References: <20220213141649.1115987-1-15330273260@189.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,FROM_LOCAL_DIGITS, FROM_LOCAL_HEX,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RDNS_NONE,SPF_HELO_NONE,SPOOFED_FREEMAIL_NO_RDNS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: suijingfeng This board has a VGA output and a DVI output, the VGA is connected to the DVO0 of the display controller and the DVI is connected to DVO1 of the display controller. +------+ +-----------------------------------+ | DDR4 | | +-------------------+ | +------+ | | PCIe Root complex | LS7A1000 | || MC0 | +--++---------++----+ | +----------+ HT 3.0 | || || | | LS3A4000 |<-------->| +---++---+ +--++--+ +---------+ +------+ | CPU |<-------->| | GC1000 | | LSDC |<-->| DDR3 MC |<->| VRAM | +----------+ | +--------+ +-+--+-+ +---------+ +------+ || MC1 +---------------|--|----------------+ +------+ | | | DDR4 | +-------+ DVO0 | | DVO1 +------+ +------+ VGA <--|ADV7125|<--------+ +-------->|TFP410|--> DVI/HDMI +-------+ +------+ Signed-off-by: suijingfeng Signed-off-by: Sui Jingfeng <15330273260@189.cn> --- .../boot/dts/loongson/ls3a4000_7a1000_evb.dts | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 arch/mips/boot/dts/loongson/ls3a4000_7a1000_evb.dts diff --git a/arch/mips/boot/dts/loongson/ls3a4000_7a1000_evb.dts b/arch/mips/boot/dts/loongson/ls3a4000_7a1000_evb.dts new file mode 100644 index 000000000000..38abe8249e05 --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls3a4000_7a1000_evb.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "loongson64g-package.dtsi" +#include "ls7a-pch.dtsi" + +/ { + model = "LS3A4000_7A1000_EVB_BOARD_V1_4"; +}; + +&package0 { + htvec: interrupt-controller@efdfb000080 { + compatible = "loongson,htvec-1.0"; + reg = <0xefd 0xfb000080 0x40>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&liointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <29 IRQ_TYPE_LEVEL_HIGH>, + <30 IRQ_TYPE_LEVEL_HIGH>, + <31 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&pch { + msi: msi-controller@2ff00000 { + compatible = "loongson,pch-msi-1.0"; + reg = <0 0x2ff00000 0 0x8>; + interrupt-controller; + msi-controller; + loongson,msi-base-vec = <64>; + loongson,msi-num-vecs = <192>; + interrupt-parent = <&htvec>; + }; +}; + +&lsdc { + output-ports = <&dvo0 &dvo1>; + + #address-cells = <1>; + #size-cells = <0>; + + dvo0: dvo@0 { + reg = <0>; + connector = "vga-connector"; + status = "okay"; + }; + + dvo1: dvo@1 { + reg = <1>; + connector = "dvi-connector"; + digital; + status = "okay"; + }; +}; -- 2.25.1