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From:   Gregory CLEMENT <gregory.clement@bootlin.com>
To:     Pali =?utf-8?Q?Roh=C3=A1r?= <pali@kernel.org>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Rob Herring <robh+dt@kernel.org>,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
        Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>,
        Marek =?utf-8?Q?Beh=C3=BAn?= <kabel@kernel.org>,
        Russell King <rmk+kernel@armlinux.org.uk>,
        Andrew Lunn <andrew@lunn.ch>
Cc:     linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 11/11] ARM: dts: armada-385.dtsi: Add definitions for
 PCIe legacy INTx interrupts
In-Reply-To: <20220112151814.24361-12-pali@kernel.org>
References: <20220105150239.9628-1-pali@kernel.org>
 <20220112151814.24361-1-pali@kernel.org>
 <20220112151814.24361-12-pali@kernel.org>
Date:   Mon, 14 Feb 2022 16:07:13 +0100
Message-ID: <87wnhxjxlq.fsf@BL-laptop>
MIME-Version: 1.0
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Precedence: bulk

Hello Pali,

> With this change legacy INTA, INTB, INTC and INTD interrupts are reported
> separately and not mixed into one Linux virq source anymore.
>
> Signed-off-by: Pali Roh=C3=A1r <pali@kernel.org>
> ---
>  arch/arm/boot/dts/armada-385.dtsi | 52 ++++++++++++++++++++++++++-----

Is there any reason for not doing the same change in armada-380.dtsi ?

Gr=C3=A9gory

>  1 file changed, 44 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada=
-385.dtsi
> index f0022d10c715..83392b92dae2 100644
> --- a/arch/arm/boot/dts/armada-385.dtsi
> +++ b/arch/arm/boot/dts/armada-385.dtsi
> @@ -69,16 +69,25 @@
>  				reg =3D <0x0800 0 0 0 0>;
>  				#address-cells =3D <3>;
>  				#size-cells =3D <2>;
> +				interrupt-names =3D "intx";
> +				interrupts-extended =3D <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
>  				#interrupt-cells =3D <1>;
>  				ranges =3D <0x82000000 0 0 0x82000000 0x1 0 1 0
>  					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
>  				bus-range =3D <0x00 0xff>;
> -				interrupt-map-mask =3D <0 0 0 0>;
> -				interrupt-map =3D <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-map-mask =3D <0 0 0 7>;
> +				interrupt-map =3D <0 0 0 1 &pcie1_intc 0>,
> +						<0 0 0 2 &pcie1_intc 1>,
> +						<0 0 0 3 &pcie1_intc 2>,
> +						<0 0 0 4 &pcie1_intc 3>;
>  				marvell,pcie-port =3D <0>;
>  				marvell,pcie-lane =3D <0>;
>  				clocks =3D <&gateclk 8>;
>  				status =3D "disabled";
> +				pcie1_intc: interrupt-controller {
> +					interrupt-controller;
> +					#interrupt-cells =3D <1>;
> +				};
>  			};
>=20=20
>  			/* x1 port */
> @@ -88,16 +97,25 @@
>  				reg =3D <0x1000 0 0 0 0>;
>  				#address-cells =3D <3>;
>  				#size-cells =3D <2>;
> +				interrupt-names =3D "intx";
> +				interrupts-extended =3D <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
>  				#interrupt-cells =3D <1>;
>  				ranges =3D <0x82000000 0 0 0x82000000 0x2 0 1 0
>  					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
>  				bus-range =3D <0x00 0xff>;
> -				interrupt-map-mask =3D <0 0 0 0>;
> -				interrupt-map =3D <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-map-mask =3D <0 0 0 7>;
> +				interrupt-map =3D <0 0 0 1 &pcie2_intc 0>,
> +						<0 0 0 2 &pcie2_intc 1>,
> +						<0 0 0 3 &pcie2_intc 2>,
> +						<0 0 0 4 &pcie2_intc 3>;
>  				marvell,pcie-port =3D <1>;
>  				marvell,pcie-lane =3D <0>;
>  				clocks =3D <&gateclk 5>;
>  				status =3D "disabled";
> +				pcie2_intc: interrupt-controller {
> +					interrupt-controller;
> +					#interrupt-cells =3D <1>;
> +				};
>  			};
>=20=20
>  			/* x1 port */
> @@ -107,16 +125,25 @@
>  				reg =3D <0x1800 0 0 0 0>;
>  				#address-cells =3D <3>;
>  				#size-cells =3D <2>;
> +				interrupt-names =3D "intx";
> +				interrupts-extended =3D <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
>  				#interrupt-cells =3D <1>;
>  				ranges =3D <0x82000000 0 0 0x82000000 0x3 0 1 0
>  					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
>  				bus-range =3D <0x00 0xff>;
> -				interrupt-map-mask =3D <0 0 0 0>;
> -				interrupt-map =3D <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-map-mask =3D <0 0 0 7>;
> +				interrupt-map =3D <0 0 0 1 &pcie3_intc 0>,
> +						<0 0 0 2 &pcie3_intc 1>,
> +						<0 0 0 3 &pcie3_intc 2>,
> +						<0 0 0 4 &pcie3_intc 3>;
>  				marvell,pcie-port =3D <2>;
>  				marvell,pcie-lane =3D <0>;
>  				clocks =3D <&gateclk 6>;
>  				status =3D "disabled";
> +				pcie3_intc: interrupt-controller {
> +					interrupt-controller;
> +					#interrupt-cells =3D <1>;
> +				};
>  			};
>=20=20
>  			/*
> @@ -129,16 +156,25 @@
>  				reg =3D <0x2000 0 0 0 0>;
>  				#address-cells =3D <3>;
>  				#size-cells =3D <2>;
> +				interrupt-names =3D "intx";
> +				interrupts-extended =3D <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
>  				#interrupt-cells =3D <1>;
>  				ranges =3D <0x82000000 0 0 0x82000000 0x4 0 1 0
>  					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
>  				bus-range =3D <0x00 0xff>;
> -				interrupt-map-mask =3D <0 0 0 0>;
> -				interrupt-map =3D <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-map-mask =3D <0 0 0 7>;
> +				interrupt-map =3D <0 0 0 1 &pcie4_intc 0>,
> +						<0 0 0 2 &pcie4_intc 1>,
> +						<0 0 0 3 &pcie4_intc 2>,
> +						<0 0 0 4 &pcie4_intc 3>;
>  				marvell,pcie-port =3D <3>;
>  				marvell,pcie-lane =3D <0>;
>  				clocks =3D <&gateclk 7>;
>  				status =3D "disabled";
> +				pcie4_intc: interrupt-controller {
> +					interrupt-controller;
> +					#interrupt-cells =3D <1>;
> +				};
>  			};
>  		};
>  	};
> --=20
> 2.20.1
>

--=20
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com