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From:   "Wu, Hao" <hao.wu@intel.com>
To:     "Zhang, Tianfei" <tianfei.zhang@intel.com>,
        "trix@redhat.com" <trix@redhat.com>,
        "mdf@kernel.org" <mdf@kernel.org>,
        "Xu, Yilun" <yilun.xu@intel.com>,
        "linux-fpga@vger.kernel.org" <linux-fpga@vger.kernel.org>,
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        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
CC:     "corbet@lwn.net" <corbet@lwn.net>,
        Matthew Gerlach <matthew.gerlach@linux.intel.com>
Subject: Re: [PATCH v1 3/7] fpga: dfl: Allow for ports with no local bar
 space.
Thread-Topic: [PATCH v1 3/7] fpga: dfl: Allow for ports with no local bar
 space.
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Date:   Wed, 16 Feb 2022 03:38:22 +0000
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 <20220214112619.219761-4-tianfei.zhang@intel.com>
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> Subject: [PATCH v1 3/7] fpga: dfl: Allow for ports with no local bar spac=
e.
>=20
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>=20
> From a fpga partial reconfiguration standpoint, a port
> may not be connected any local BAR space.  The port could
> be connected to a different PCIe Physical Function (PF) or
> Virtual Function (VF), in which case another driver instance
> would manage the endpoint.
>=20
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
> ---
>  drivers/fpga/dfl-pci.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>=20
> diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
> index 4d68719e608f..8abd9b408403 100644
> --- a/drivers/fpga/dfl-pci.c
> +++ b/drivers/fpga/dfl-pci.c
> @@ -243,6 +243,7 @@ static int find_dfls_by_default(struct pci_dev *pcide=
v,
>  		v =3D readq(base + FME_HDR_CAP);
>  		port_num =3D FIELD_GET(FME_CAP_NUM_PORTS, v);
>=20
> +		dev_info(&pcidev->dev, "port_num =3D %d\n", port_num);

Do we really need this info here? in FME there is one sysfs interface for p=
ort num.

>  		WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM);
>=20
>  		for (i =3D 0; i < port_num; i++) {
> @@ -258,6 +259,13 @@ static int find_dfls_by_default(struct pci_dev *pcid=
ev,
>  			 */
>  			bar =3D FIELD_GET(FME_PORT_OFST_BAR_ID, v);
>  			offset =3D FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
> +			if (bar >=3D PCI_STD_NUM_BARS) {
> +				dev_info(&pcidev->dev, "skipping port without
> local BAR space %d\n",
> +					 bar);
> +				continue;

Is this change for IOFS? From patch #1, we have FME and PORT on PF0, so
we should have a BAR for PORT on PF0, is my understanding correct?

Thanks
Hao

> +			} else {
> +				dev_info(&pcidev->dev, "BAR %d offset %u\n",
> bar, offset);
> +			}
>  			start =3D pci_resource_start(pcidev, bar) + offset;
>  			len =3D pci_resource_len(pcidev, bar) - offset;
>=20
> --
> 2.17.1