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Tue, 15 Feb 2022 18:39:56 -0800 Received: from [10.111.168.21] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 15 Feb 2022 18:39:54 -0800 Message-ID: <4ab99ff6-39c4-2ec8-4d20-277524cb32e4@quicinc.com> Date: Tue, 15 Feb 2022 18:39:52 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.5.1 Subject: Re: [PATCH v2 1/2] drm/msm/dpu: Add INTF_5 interrupts Content-Language: en-US To: Bjorn Andersson , Rob Clark , Dmitry Baryshkov CC: , , , References: <20220215043353.1256754-1-bjorn.andersson@linaro.org> From: Abhinav Kumar In-Reply-To: <20220215043353.1256754-1-bjorn.andersson@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,RDNS_NONE,SPF_HELO_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2/14/2022 8:33 PM, Bjorn Andersson wrote: > SC8180x has the eDP controller wired up to INTF_5, so add the interrupt > register block for this interface to the list. > > Signed-off-by: Bjorn Andersson Reviewed-by: Abhinav Kumar > --- > > Changes since v1: > - None > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 6 ++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 1 + > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > index a77a5eaa78ad..dd2161e7bdb6 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > @@ -23,6 +23,7 @@ > #define MDP_INTF_2_OFF 0x6B000 > #define MDP_INTF_3_OFF 0x6B800 > #define MDP_INTF_4_OFF 0x6C000 > +#define MDP_INTF_5_OFF 0x6C800 > #define MDP_AD4_0_OFF 0x7C000 > #define MDP_AD4_1_OFF 0x7D000 > #define MDP_AD4_INTR_EN_OFF 0x41c > @@ -93,6 +94,11 @@ static const struct dpu_intr_reg dpu_intr_set[] = { > MDP_INTF_4_OFF+INTF_INTR_EN, > MDP_INTF_4_OFF+INTF_INTR_STATUS > }, > + { > + MDP_INTF_5_OFF+INTF_INTR_CLEAR, > + MDP_INTF_5_OFF+INTF_INTR_EN, > + MDP_INTF_5_OFF+INTF_INTR_STATUS > + }, > { > MDP_AD4_0_OFF + MDP_AD4_INTR_CLEAR_OFF, > MDP_AD4_0_OFF + MDP_AD4_INTR_EN_OFF, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h > index 1ab75cccd145..37379966d8ec 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h > @@ -22,6 +22,7 @@ enum dpu_hw_intr_reg { > MDP_INTF2_INTR, > MDP_INTF3_INTR, > MDP_INTF4_INTR, > + MDP_INTF5_INTR, > MDP_AD4_0_INTR, > MDP_AD4_1_INTR, > MDP_INTF0_7xxx_INTR,