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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id c68sm5431002pga.1.2022.02.16.05.28.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Feb 2022 05:28:42 -0800 (PST) From: Shawn Guo To: Marc Zyngier , Thomas Gleixner Cc: Maulik Shah , Bjorn Andersson , Lorenzo Pieralisi , Sudeep Holla , "Rafael J . Wysocki" , Daniel Lezcano , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH v5 0/3] Add Qualcomm MPM irqchip driver support Date: Wed, 16 Feb 2022 21:28:27 +0800 Message-Id: <20220216132830.32490-1-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It starts from updating cpuidle-psci driver to send CPU_CLUSTER_PM_ENTER notification, and then adds DT binding and driver support for Qualcomm MPM (MSM Power Manager) interrupt controller. Changes for v5: - Drop inline attributes and let compiler to decide - Use _irqsave/_irqrestore flavour for spin lock - Assignment on a single for irq_resolve_mapping() call - Add documentation to explain vMPM ownership transition - Move MPM pin map data into device tree and so use a generic compatible - Drop the code that counts CPUs in PM and use CPU_CLUSTER_PM_ENTER notification instead Changes for v4: - Add the missing include of to fix build errors on arm architecture. - Leave IRQCHIP_PLATFORM_DRIVER infrastructural unchanged, and use of_find_device_by_node() to get platform_device pointer. Changes for v3: - Support module build - Use relaxed accessors - Add barrier call to ensure MMIO write completes - Use d->chip_data to pass driver private data - Use raw spinlock - USe BIT() for bit shift - Create a single irq domain to cover both types of MPM pins - Call irq_resolve_mapping() to find out Linux irq number - Save the use of ternary conditional operator and use switch/case for .irq_set_type call - Drop unnecessary .irq_disable hook - Align qcom_mpm_chip and qcom_mpm_ops members vertically - Use helper irq_domain_translate_twocell() - Move mailbox requesting forward in probe function - Improve the documentation on qcm2290_gic_pins[] - Use IRQCHIP_PLATFORM_DRIVER infrastructural - Use cpu_pm notifier instead of .suspend_late hook to write MPM for sleep, so that MPM can be set up for both suspend and idle context. The TIMER0/1 setup is currently omitted for idle use case though, as I haven't been able to successfully test the idle context. Shawn Guo (3): cpuidle: psci: Call cpu_cluster_pm_enter() on the last CPU dt-bindings: interrupt-controller: Add Qualcomm MPM support irqchip: Add Qualcomm MPM controller driver .../interrupt-controller/qcom,mpm.yaml | 94 ++++ drivers/cpuidle/cpuidle-psci.c | 13 + drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/qcom-mpm.c | 440 ++++++++++++++++++ 5 files changed, 556 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml create mode 100644 drivers/irqchip/qcom-mpm.c -- 2.17.1