Received: by 2002:a05:6a10:7420:0:0:0:0 with SMTP id hk32csp277617pxb; Thu, 17 Feb 2022 04:03:20 -0800 (PST) X-Google-Smtp-Source: ABdhPJz/SsB22xZizcLgzMpb87VLcj8HJNwID2jBXPy9WAdcBzxn12lzCg8hxuBpQmcYZu0+tFk5 X-Received: by 2002:a17:906:4d05:b0:6cf:d1bf:3184 with SMTP id r5-20020a1709064d0500b006cfd1bf3184mr2110869eju.721.1645099399860; Thu, 17 Feb 2022 04:03:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1645099399; cv=none; d=google.com; s=arc-20160816; b=WgGb0hoBi/HbfV1qMGBiC7RkE+be3WD28JLiiDu3p6GdOqjleGqRrXK3XoxfJ0CckY XrG9qx+n2SyXM3um0hARmEWmSeH1xmGFEHzfwhDWV0hCI4z3WSjE73l4xf8U6AjO8BSo NGcgCdSG2C0M4TUQ2kRRMbcizNvNPzumTEabfPFAXlWrHwiOfNoYsk/OnKOLfd7P89n6 G/+ohH4i12a8qhdq65fRovzXUwg5s/69WDN6McKsDcJ3YBKehC3PwmflMq05o/RI0x8D tqUgO6s3OlWZKQ3uYUFAnNXVcMgP2Fy5HQPP3rCyuuTXK2ApEOlzbg8/vwbQcAp7YDnz H31A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from :dkim-signature; bh=H9Eo2ff2mtGTaLBOP560+TItjLIJaqXZeafS5+0V7ys=; b=AcRChVOg//OlJtgxEBjPbFcL1/6eEH0NeamaV5j05BkgWnp2FTTXn4CMa9Chs8P1hU 4zJNeDIl5aMeXvTdOMwBK7TJc1XbQhgxKmwzgI1PZd0WTJbJYvyaI5lnVTjg0jYS4LwZ HRP50IknlzLekPoqw2+fBkbMMSYTY8fRis4VDKJUXnapScXAJOR241PC/p2ecXpTJts5 rE3i+DSG92tXCcIOdAsDCCKJ/zNpFMX9W4uPtksXgRO7UtpXyCI+IPs6YD/O0j+1R0P4 1+tA1kOVgrQ8H1KIucqbKte1FjO3T6+nTUhHNHiO7M61uNikgshHZFVoiwNVOZKsIBN2 6zxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=MpFHumzG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id di20si1963559ejc.397.2022.02.17.04.02.44; Thu, 17 Feb 2022 04:03:19 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=MpFHumzG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234590AbiBQF6X (ORCPT + 99 others); Thu, 17 Feb 2022 00:58:23 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234507AbiBQF6W (ORCPT ); Thu, 17 Feb 2022 00:58:22 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C3CE629926E; Wed, 16 Feb 2022 21:58:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645077489; x=1676613489; h=from:to:cc:subject:date:message-id:mime-version; bh=H9Eo2ff2mtGTaLBOP560+TItjLIJaqXZeafS5+0V7ys=; b=MpFHumzGO2X6gjQw9hBbCrzR+KvvdpIRiYopZW4GNmZSiqhURvN8EAed zMdXo7BVlx/jusaV3DCdUUjG64wjOSpwadufZDRoPjTpXAb9yUR6heLZR 4tEusd6sPMHZyRY8qrRpV1WAIP3298XCzMMX4i3c5hLSSxI88bHPEOdZ+ U=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 16 Feb 2022 21:58:08 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2022 21:58:07 -0800 Received: from nalasex01b.na.qualcomm.com (10.47.209.197) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Wed, 16 Feb 2022 21:58:07 -0800 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Wed, 16 Feb 2022 21:58:01 -0800 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , , Linus Walleij , CC: Srinivasa Rao Mandadapu Subject: [RESEND v7 0/7] Add pin control support for lpass sc7280 Date: Thu, 17 Feb 2022 11:27:40 +0530 Message-ID: <1645077467-6831-1-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch series is to split lpass variant common pin control functions and SoC specific functions and to add lpass sc7280 pincontrol support. It also Adds dt-bindings for lpass sc7280 lpass lpi pincontrol. Changes Since V6: -- Update conditional clock voting to optional clock voting. -- Update Kconfig depends on field with select. -- Fix typo errors. Changes Since V5: -- Create new patch by updating macro name to lpi specific. -- Create new patch by updating lpi pin group structure with core group_desc structure. -- Fix typo errors. -- Sort macros in the make file and configuration file. Changes Since V4: -- Update commit message and description of the chip specific extraction patch. -- Sort macros in kconfig and makefile. -- Update optional clock voting to conditional clock voting. -- Fix typo errors. -- Move to quicinc domain email id's. Changes Since V3: -- Update separate Kconfig fields for sm8250 and sc7280. -- Update module license and description. -- Move static variables to corresponding .c files from header file. Changes Since V2: -- Add new dt-bindings for sc7280 lpi driver. -- Make clock voting change as separate patch. -- Split existing pincontrol driver and make common functions as part of separate file. -- Rename lpass pincontrol lpi dt-bindings to sm8250 specific dt-bindings Changes Since V1: -- Make lpi pinctrl variant data structure as constant -- Add appropriate commit message -- Change signedoff by sequence. Srinivasa Rao Mandadapu (7): dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings pinctrl: qcom: Update macro name to LPI specific pinctrl: qcom: Update lpi pin group structure pinctrl: qcom: Extract chip specific LPASS LPI code pinctrl: qcom: Add SC7280 lpass pin configuration pinctrl: qcom: Update clock voting as optional Tested this on SM8250 MTP with WSA and WCD codecs. Tested-by: Srinivas Kandagatla .../bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 133 ----------- .../pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 115 ++++++++++ .../pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 133 +++++++++++ drivers/pinctrl/qcom/Kconfig | 16 ++ drivers/pinctrl/qcom/Makefile | 2 + drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 245 +-------------------- drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 86 ++++++++ drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 168 ++++++++++++++ drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 166 ++++++++++++++ 9 files changed, 696 insertions(+), 368 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.h create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c -- 2.7.4