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Subject: Re: [PATCH v2 7/7] clk: qcom: Add SDX65 APCS clock controller support
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
        linux-clk@vger.kernel.org,
        Rohit Agarwal <quic_rohiagar@quicinc.com>
To:     Rohit Agarwal <quic_rohiagar@quicinc.com>, agross@kernel.org,
        bjorn.andersson@linaro.org, manivannan.sadhasivam@linaro.org,
        mturquette@baylibre.com
Date:   Thu, 17 Feb 2022 16:21:53 -0800
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Message-Id: <20220218002155.AD55BC340E8@smtp.kernel.org>
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Quoting Rohit Agarwal (2022-02-15 02:09:13)
> Add a driver config support for the SDX65 APCS clock controller. It is pa=
rt

Maybe "Add a driver config" is a little strong for the patch contents.
More like "Update APCS Kconfig to reflect support for another SoC".

> of the APCS hardware block, which among other things implements a combined
> mux and half integer divider functionality. The APCS clock controller has=
 3
> parent clocks:
>=20
> 1. Board XO
> 2. Fixed rate GPLL0
> 3. A7 PLL
>=20
> This is required for enabling CPU frequency scaling on SDX65-based
> platforms.
>=20
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>