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[209.85.218.48]) by smtp.gmail.com with ESMTPSA id q14sm4055398edd.54.2022.02.17.17.09.31 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Feb 2022 17:09:31 -0800 (PST) Received: by mail-ej1-f48.google.com with SMTP id hw13so11217224ejc.9 for ; Thu, 17 Feb 2022 17:09:31 -0800 (PST) X-Received: by 2002:a5d:64ef:0:b0:1e3:1e05:d042 with SMTP id g15-20020a5d64ef000000b001e31e05d042mr4049131wri.679.1645146213585; Thu, 17 Feb 2022 17:03:33 -0800 (PST) MIME-Version: 1.0 References: <1644494255-6632-1-git-send-email-quic_sbillaka@quicinc.com> <1644494255-6632-3-git-send-email-quic_sbillaka@quicinc.com> In-Reply-To: <1644494255-6632-3-git-send-email-quic_sbillaka@quicinc.com> From: Doug Anderson Date: Thu, 17 Feb 2022 17:03:13 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 2/5] arm64: dts: qcom: sc7280: Add support for eDP panel on CRD To: Sankeerth Billakanti Cc: dri-devel , linux-arm-msm , freedreno , LKML , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Andy Gross , Bjorn Andersson , Rob Herring , Rob Clark , Sean Paul , Stephen Boyd , Krzysztof Kozlowski , Thierry Reding , Sam Ravnborg , David Airlie , Daniel Vetter , quic_kalyant@quicinc.com, quic_abhinavk@quicinc.com, quic_khsieh@quicinc.com, quic_mkrishn@quicinc.com, quic_vproddut@quicinc.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thu, Feb 10, 2022 at 3:58 AM Sankeerth Billakanti wrote: > > + backlight_3v3_regulator: backlight-3v3-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "backlight_3v3_regulator"; > + > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + > + gpio = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&edp_bl_power>; > + }; So I'm pretty sure that this is wrong and what you had on a previous patch was more correct. Specifically the PMIC's GPIO 7 truly _is_ an enable pin for the backlight. In the schematics I see it's named as "PMIC_EDP_BL_EN" and is essentially the same net as "EDP_BL_EN". This is distinct from the backlight _regulator_ that is named VREG_EDP_BP. I believe the VREG_EDP_BP is essentially sourced directly from PPVAR_SYS. That's how it works on herobrine and I believe that CRD is the same. You currently don't model ppvar_sys, but it's basically just a variable-voltage rail that could be provided somewhat directly from the battery or could be provided from Type C components. I believe that the panel backlight is designed to handle this fairly wide voltage range and it's done this way to get the best efficiency. So personally I'd prefer if you do something like herobrine and model PPVAR_SYS. Then the backlight can use ppvar_sys as its regulator and you can go back to providing this as an "enable" pin for the backlight. I know, technically it doesn't _really_ matter, but it's nice to model it more correctly.