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Peter Anvin" , Dave Hansen , Yazen Ghannam Subject: Re: [RFC PATCH 1/2] x86/mce: Handle AMD threshold interrupt storms Message-ID: References: <20220217141609.119453-1-Smita.KoralahalliChannabasappa@amd.com> <20220217141609.119453-2-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Feb 17, 2022 at 09:28:09AM -0800, Luck, Tony wrote: > I've been sitting on some partially done patches to re-work > storm handling for Intel ... which rips out all the existing > storm bits and replaces with something all new. I'll post the > 2-part series as replies to this. Which begs the obvious question: how much of that code can be shared between the two? -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette