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References: <20220131220518.GA515079@bhelgaas> <bac4cc7e-f81e-82e6-9b60-e5e3199637d7@ti.com>
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From:   Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Fri, 18 Feb 2022 14:13:44 +0100
Message-ID: <CAH9NwWcChBLEwLrzUEcvh7EXtjaEBe5rZo0gHNnzXnaV9p5QGA@mail.gmail.com>
Subject: Re: [PATCH] PCI: cadence: respond to received PTM Requests
To:     Kishon Vijay Abraham I <kishon@ti.com>
Cc:     Bjorn Helgaas <helgaas@kernel.org>,
        LKML <linux-kernel@vger.kernel.org>,
        Tom Joseph <tjoseph@cadence.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Rob Herring <robh@kernel.org>,
        =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= <kw@linux.com>,
        Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org
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Hi Bjorn,

Am Fr., 18. Feb. 2022 um 11:56 Uhr schrieb Kishon Vijay Abraham I
<kishon@ti.com>:
>
> Hi Bjorn,
>
> On 01/02/22 3:35 am, Bjorn Helgaas wrote:
> > Update subject line to match previous conventions ("git log --oneline
> > drivers/pci/controller/cadence/pcie-cadence-host.c" to see).
> >
> > On Mon, Jan 31, 2022 at 01:08:27PM +0100, Christian Gmeiner wrote:
> >> This enables the Controller [RP] to automatically respond
> >> with Response/ResponseD messages.
> >
> > Update to imperative mood, e.g., "Enable Controller to ...":
> >
> >   https://chris.beams.io/posts/git-commit/
> >   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/maintainer-tip.rst?id=v5.16#n134
> >
> >> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
> >> ---
> >>  drivers/pci/controller/cadence/pcie-cadence-host.c | 10 ++++++++++
> >>  drivers/pci/controller/cadence/pcie-cadence.h      |  4 ++++
> >>  2 files changed, 14 insertions(+)
> >>
> >> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> >> index fb96d37a135c..940c7dd701d6 100644
> >> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> >> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> >> @@ -123,6 +123,14 @@ static int cdns_pcie_retrain(struct cdns_pcie *pcie)
> >>      return ret;
> >>  }
> >>
> >> +static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie)
> >> +{
> >> +    u32 val;
> >> +
> >> +    val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_PTM_CTRL);
> >> +    cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN);
> >
> > I assume this is some device-specific enable bit that is effectively
> > ANDed with PCI_PTM_CTRL_ENABLE in the Precision Time Measurement
> > Capability?
>
> That's correct. This bit enables Controller [RP] to respond to the received PTM
> Requests.
>

With that information is it okay for you that I send a V2 of this
patch with an improved commit message or do
you see any other problems that I need to take into account?

-- 
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info/privacypolicy