Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   Rohit Agarwal <quic_rohiagar@quicinc.com>
To:     agross@kernel.org, bjorn.andersson@linaro.org,
        mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
        jassisinghbrar@gmail.com, manivannan.sadhasivam@linaro.org
Cc:     linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        Rohit Agarwal <quic_rohiagar@quicinc.com>
Subject: [PATCH v3 7/7] clk: qcom: Add SDX65 APCS clock controller support
Date:   Mon, 21 Feb 2022 10:52:33 +0530
Message-Id: <1645420953-21176-8-git-send-email-quic_rohiagar@quicinc.com>
In-Reply-To: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com>
References: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com>
Precedence: bulk

Update APCS Kconfig to reflect support for SDX65
APCS clock controller.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 drivers/clk/qcom/Kconfig | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 5159a1d..a2fa9af 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -55,13 +55,13 @@ config QCOM_CLK_APCC_MSM8996
 	  drivers for dynamic power management.
 
 config QCOM_CLK_APCS_SDX55
-	tristate "SDX55 APCS Clock Controller"
+	tristate "SDX55 and SDX65 APCS Clock Controller"
 	depends on QCOM_APCS_IPC || COMPILE_TEST
 	help
-	  Support for the APCS Clock Controller on SDX55 platform. The
+	  Support for the APCS Clock Controller on SDX55, SDX65 platform. The
 	  APCS is managing the mux and divider which feeds the CPUs.
 	  Say Y if you want to support CPU frequency scaling on devices
-	  such as SDX55.
+	  such as SDX55, SDX65.
 
 config QCOM_CLK_RPM
 	tristate "RPM based Clock Controller"
-- 
2.7.4