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From:   Rohit Agarwal <quic_rohiagar@quicinc.com>
To:     agross@kernel.org, bjorn.andersson@linaro.org,
        mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
        jassisinghbrar@gmail.com, manivannan.sadhasivam@linaro.org
Cc:     linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        Rohit Agarwal <quic_rohiagar@quicinc.com>
Subject: [PATCH v3 0/7] Add APCS support for SDX65
Date:   Mon, 21 Feb 2022 10:52:26 +0530
Message-Id: <1645420953-21176-1-git-send-email-quic_rohiagar@quicinc.com>
Precedence: bulk

Hello,

Changes from v2:
 - Addressed Stephen's comments and made necessary changes.
 - Rebased on top

Changes from v1:
 - Addressed Mani's comments and made necessary changes.
 - Removed the last patch from the series as it became redundant after making changes.

This series adds APCS mailbox and clock support for SDX65. The APCS IP
in SDX65 provides IPC and clock functionalities. Hence, mailbox support
is added to the "qcom-apcs-ipc-mailbox" driver and a dedicated clock
driver "apcs-sdx65" is added.

Thanks,
Rohit

Rohit Agarwal (7):
  dt-bindings: mailbox: Add binding for SDX65 APCS
  mailbox: qcom: Add support for SDX65 APCS IPC
  dt-bindings: clock: Add A7 PLL binding for SDX65
  clk: qcom: Add A7 PLL support for SDX65
  ARM: dts: qcom: sdx65: Add support for A7 PLL clock
  ARM: dts: qcom: sdx65: Add support for APCS block
  clk: qcom: Add SDX65 APCS clock controller support

 Documentation/devicetree/bindings/clock/qcom,a7pll.yaml |  3 ++-
 .../bindings/mailbox/qcom,apcs-kpss-global.yaml         |  1 +
 arch/arm/boot/dts/qcom-sdx65.dtsi                       | 17 +++++++++++++++++
 drivers/clk/qcom/Kconfig                                | 12 ++++++------
 drivers/clk/qcom/a7-pll.c                               |  1 +
 drivers/mailbox/qcom-apcs-ipc-mailbox.c                 |  5 +++++
 6 files changed, 32 insertions(+), 7 deletions(-)

-- 
2.7.4