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Date:   Mon, 21 Feb 2022 16:43:07 +0000 (GMT)
From:   "Maciej W. Rozycki" <macro@orcam.me.uk>
To:     Jiaxun Yang <jiaxun.yang@flygoat.com>
cc:     linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
        chenhuacai@kernel.org, tsbogend@alpha.franken.de
Subject: Re: [RFC PATCH 3/3] MIPS: io.h: Remove barriers before MMIO accessors
 for CPU without WB
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On Mon, 21 Feb 2022, Jiaxun Yang wrote:

> Commit 3d474da ("MIPS: Enforce strong ordering for MMIO accessors")

 Please follow the canonical commit reference format including a 12-digit 
hexadecimal hash reference (`scripts/checkpatch.pl' would have pointed it 
out).

> SYNC based barrier is very heavy on Loongson and MTI cores as it will
> issue a SYNC command on their bus and invalidate all present instrutions
> in pipeline. We should generally avoid that.

 Use whatever lighterweight barrier instruction you have available for 
your specific platforms then that fulfills the ordering enforcement 
required here for your specific platforms of concern that you have 
identified and know well rather than across the board.  The reason for 
this is this is an optimisation and the default barrier model needs to 
ensure correct execution with any implementation.

  Maciej