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Date:   Mon, 21 Feb 2022 22:25:58 +0530
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Subject: Re: [v1 1/2] clk: qcom: gdsc: Use the default transition delay for
 GDSCs
Content-Language: en-US
To:     Stephen Boyd <sboyd@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>
Cc:     Michael Turquette <mturquette@baylibre.com>,
        Rajendra Nayak <rnayak@codeaurora.org>,
        linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
References: <20220209172513.17873-1-tdas@codeaurora.org>
 <YgRBnExwlzI+lPlR@builder.lan> <20220210072842.3E796C004E1@smtp.kernel.org>
From:   Taniya Das <tdas@codeaurora.org>
In-Reply-To: <20220210072842.3E796C004E1@smtp.kernel.org>
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Hi Stephen, Bjorn,

Thanks for your comments.

On 2/10/2022 12:58 PM, Stephen Boyd wrote:
> Quoting Bjorn Andersson (2022-02-09 14:35:08)
>> On Wed 09 Feb 11:25 CST 2022, Taniya Das wrote:
>>
>>> Do not update the transition delay and use the default reset values.
>>>
>>> Fixes: 45dd0e55317cc ("clk: qcom: Add support for GDSCs)
>>> Signed-off-by: Taniya Das <tdas@codeaurora.org>
>>> ---
>>>   drivers/clk/qcom/gdsc.c | 6 +++++-
>>>   drivers/clk/qcom/gdsc.h | 1 +
>>>   2 files changed, 6 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
>>> index 7e1dd8ccfa38..e7b213450640 100644
>>> --- a/drivers/clk/qcom/gdsc.c
>>> +++ b/drivers/clk/qcom/gdsc.c
>>> @@ -380,7 +380,11 @@ static int gdsc_init(struct gdsc *sc)
>>>         */
>>>        mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
>>>               EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
>>> -     val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
>>> +
>>> +     regmap_read(sc->regmap, sc->gdscr, &val);
>>> +
>>> +     if (!(sc->flags & DEFAULT_TRANSITION_DELAY))
>>
>> I dug a little bit more into this and noticed that on various platforms
>> CLK_DIS_WAIT_VAL for the GPU_CX GDSC is supposed to be 8 (whereas both
>> hw default and CLK_DIS_WAIT_VAL is 2).
>>

Yes, only for certain GPU_CC these would be updated and that too in case 
the design team suggests. Downstream we would set the value from probe 
itself, or we can pick these from device tree as required and suggested.

>> I'm not able to find anything helpful in the git log describing what the
>> value does, but it seems that a "just use hw default" flag won't cut it
>> for this scenario.
>>

This value is used for the number of clock cycles it would wait before 
the GDSCR ACK signals/halting the clock.

> 
> I'd prefer we invert the logic so that we don't need to litter this flag
> all over the place. I recall that the wait values were incorrect a long
> time ago on early gdsc using designs but hopefully they've been fixed
> now and we can simply use the default power on reset (POR) values.

I am okay to invert the logic, but I am not sure if they could cause any 
issues to the older targets. They were broken in HW design long back, 
but got fixed in most families of target and most GDSCs.

As mentioned if explicitly they need to be updated, it is best to do 
from the probe.
This was done in SC7180 GPUCC driver.
         /* Configure clk_dis_wait for gpu_cx_gdsc */
         regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK,
                                         8 << CLK_DIS_WAIT_SHIFT);


Please let me know if we are okay to add the invert logic.

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