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Date:   Tue, 22 Feb 2022 22:15:37 +0100
From:   Borislav Petkov <bp@alien8.de>
To:     "Koralahalli Channabasappa, Smita" <skoralah@amd.com>
Cc:     Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>,
        x86@kernel.org, linux-edac@vger.kernel.org,
        linux-kernel@vger.kernel.org, Tony Luck <tony.luck@intel.com>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        "H . Peter Anvin" <hpa@zytor.com>,
        James Morse <james.morse@arm.com>,
        Robert Richter <rric@kernel.org>,
        Yazen Ghannam <yazen.ghannam@amd.com>
Subject: Re: [PATCH v3 3/4] x86/mce, EDAC/mce_amd: Cache MCA_CONFIG[McaX] in
 struct mce_bank
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On Tue, Feb 22, 2022 at 02:47:44PM -0600, Koralahalli Channabasappa, Smita wrote:
> But what do you think of severity? Will this make an impact when handling
> panic severity levels? .. mce_severity_amd_smca().

Well, look at the code: severity grading gets called when either polling
or #MC handler gets to log an MCE. Reading an MSR costs a couple of
hundred cycles. The whole MCE logging path costs maybe a couple of
*orders* of magnitude more so that MSR read is in the noise when you
have a 4GHz CPU executing 4 billion cycles per second.

Now, that's for a single MCE.

If it were more, say 10s, 100s, 1000s MCEs, then the MSR read is the
least of your problems.

But this is me conjecturing - I'm always interested in a real proof
where it shows or it does not.

I guess what I'm trying to say is, yeah, sure, speed is mostly a good
argument. But you always need to consider at what cost you'd get that
speed. And if at all. There are other important things like keeping the
code base maintainable, readable and able to accept modifications for
new features.

So there's always this question of balance that needs to be asked...

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette