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Date:   Tue, 22 Feb 2022 08:24:09 -0800
From:   Christoph Hellwig <hch@infradead.org>
To:     Mikko Perttunen <mperttunen@nvidia.com>
Cc:     thierry.reding@gmail.com, jonathanh@nvidia.com, joro@8bytes.org,
        will@kernel.org, robh+dt@kernel.org, robin.murphy@arm.com,
        linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org,
        iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 3/9] gpu: host1x: Add context device management code
Message-ID: <YhUOKaoCA7dyAZAh@infradead.org>
References: <20220218113952.3077606-1-mperttunen@nvidia.com>
 <20220218113952.3077606-4-mperttunen@nvidia.com>
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On Fri, Feb 18, 2022 at 01:39:46PM +0200, Mikko Perttunen wrote:
> +
> +/*
> + * Due to an issue with T194 NVENC, only 38 bits can be used.
> + * Anyway, 256GiB of IOVA ought to be enough for anyone.
> + */
> +static dma_addr_t context_device_dma_mask = DMA_BIT_MASK(38);

You need a mask per device.  Please don't share the same variable
for multiple masks.

> +EXPORT_SYMBOL(host1x_context_alloc);

All this low-level code really should be EXPORT_SYMBOL_GPL.