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Date:   Thu, 24 Feb 2022 18:14:37 +0300
From:   Dan Carpenter <dan.carpenter@oracle.com>
To:     kbuild@lists.01.org, Krishna Yarlagadda <kyarlagadda@nvidia.com>,
        broonie@kernel.org, thierry.reding@gmail.com, jonathanh@nvidia.com,
        linux-spi@vger.kernel.org, linux-tegra@vger.kernel.org
Cc:     lkp@intel.com, kbuild-all@lists.01.org, skomatineni@nvidia.com,
        ldewangan@nvidia.com, robh+dt@kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        p.zabel@pengutronix.de, Krishna Yarlagadda <kyarlagadda@nvidia.com>
Subject: Re: [PATCH v2 5/5] spi: tegra210-quad: combined sequence mode
Message-ID: <202202241115.MFFaDVz5-lkp@intel.com>
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Hi Krishna,

url:    https://github.com/0day-ci/linux/commits/Krishna-Yarlagadda/Tegra-QUAD-SPI-combined-sequence-mode/20220223-015906
base:   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
config: riscv-randconfig-m031-20220222 (https://download.01.org/0day-ci/archive/20220224/202202241115.MFFaDVz5-lkp@intel.com/config)
compiler: riscv64-linux-gcc (GCC) 11.2.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

New smatch warnings:
drivers/spi/spi-tegra210-quad.c:1148 tegra_qspi_combined_seq_xfer() error: uninitialized symbol 'ret'.

vim +/ret +1148 drivers/spi/spi-tegra210-quad.c

3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1032  
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1033  static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1034  					struct spi_message *msg)
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1035  {
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1036  	bool is_first_msg = true;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1037  	struct spi_transfer *xfer;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1038  	struct spi_device *spi = msg->spi;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1039  	u8 transfer_phase = 0;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1040  	u32 cmd1 = 0, dma_ctl = 0;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1041  	int ret;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1042  	u32 address_value = 0;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1043  	u32 cmd_config = 0, addr_config = 0;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1044  	u8 cmd_value = 0, len = 0, val = 0;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1045  
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1046  	/* Enable Combined sequence mode */
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1047  	val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1048  	val |= QSPI_CMB_SEQ_EN;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1049  	tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1050  	/* Process individual transfer list */
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1051  	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1052  		switch (transfer_phase) {
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1053  		case CMD_TRANSFER:
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1054  			/* X1 SDR mode */
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1055  			cmd_config = tegra_qspi_cmd_config(false, 0,
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1056  							   xfer->len);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1057  			cmd_value = *((const u8 *)(xfer->tx_buf));
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1058  			break;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1059  		case ADDR_TRANSFER:
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1060  			len = xfer->len;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1061  			/* X1 SDR mode */
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1062  			addr_config = tegra_qspi_addr_config(false, 0,
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1063  							     xfer->len);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1064  			address_value = *((const u32 *)(xfer->tx_buf));
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1065  			break;

It's easy to imagine paths like this where ret is not set.

3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1066  		case DATA_TRANSFER:
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1067  			/* Program Command, Address value in register */
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1068  			tegra_qspi_writel(tqspi, cmd_value, QSPI_CMB_SEQ_CMD);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1069  			tegra_qspi_writel(tqspi, address_value,
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1070  					  QSPI_CMB_SEQ_ADDR);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1071  			/* Program Command and Address config in register */
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1072  			tegra_qspi_writel(tqspi, cmd_config,
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1073  					  QSPI_CMB_SEQ_CMD_CFG);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1074  			tegra_qspi_writel(tqspi, addr_config,
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1075  					  QSPI_CMB_SEQ_ADDR_CFG);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1076  
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1077  			reinit_completion(&tqspi->xfer_completion);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1078  			cmd1 = tegra_qspi_setup_transfer_one(spi, xfer,
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1079  							     is_first_msg);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1080  			ret = tegra_qspi_start_transfer_one(spi, xfer,
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1081  							    cmd1);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1082  
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1083  			if (ret < 0) {
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1084  				dev_err(tqspi->dev, "Failed to start transfer-one: %d\n",
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1085  					ret);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1086  				return ret;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1087  			}
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1088  
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1089  			is_first_msg = false;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1090  			ret = wait_for_completion_timeout
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1091  					(&tqspi->xfer_completion,
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1092  					QSPI_DMA_TIMEOUT);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1093  
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1094  			if (WARN_ON(ret == 0)) {
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1095  				dev_err(tqspi->dev, "QSPI Transfer failed with timeout: %d\n",
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1096  					ret);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1097  				if (tqspi->is_curr_dma_xfer &&
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1098  				    (tqspi->cur_direction & DATA_DIR_TX))
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1099  					dmaengine_terminate_all
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1100  						(tqspi->tx_dma_chan);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1101  
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1102  				if (tqspi->is_curr_dma_xfer &&
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1103  				    (tqspi->cur_direction & DATA_DIR_RX))
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1104  					dmaengine_terminate_all
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1105  						(tqspi->rx_dma_chan);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1106  
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1107  				/* Abort transfer by resetting pio/dma bit */
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1108  				if (!tqspi->is_curr_dma_xfer) {
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1109  					cmd1 = tegra_qspi_readl
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1110  							(tqspi,
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1111  							 QSPI_COMMAND1);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1112  					cmd1 &= ~QSPI_PIO;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1113  					tegra_qspi_writel
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1114  							(tqspi, cmd1,
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1115  							 QSPI_COMMAND1);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1116  				} else {
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1117  					dma_ctl = tegra_qspi_readl
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1118  							(tqspi,
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1119  							 QSPI_DMA_CTL);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1120  					dma_ctl &= ~QSPI_DMA_EN;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1121  					tegra_qspi_writel(tqspi, dma_ctl,
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1122  							  QSPI_DMA_CTL);
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1123  				}
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1124  
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1125  				/* Reset controller if timeout happens */
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1126  				if (device_reset(tqspi->dev) < 0)
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1127  					dev_warn_once(tqspi->dev,
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1128  						      "device reset failed\n");
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1129  				ret = -EIO;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1130  				goto exit;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1131  			}
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1132  
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1133  			if (tqspi->tx_status ||  tqspi->rx_status) {
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1134  				dev_err(tqspi->dev, "QSPI Transfer failed\n");
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1135  				tqspi->tx_status = 0;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1136  				tqspi->rx_status = 0;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1137  				ret = -EIO;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1138  				goto exit;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1139  			}
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1140  		default:
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1141  			goto exit;

Or here

3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1142  		}
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1143  		msg->actual_length += xfer->len;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1144  		transfer_phase++;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1145  	}
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1146  
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1147  exit:
3b852b330b0b83 Krishna Yarlagadda 2022-02-22 @1148  	msg->status = ret;
                                                                      ^^^

3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1149  
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1150  	return ret;
3b852b330b0b83 Krishna Yarlagadda 2022-02-22  1151  }

---
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