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[66.90.148.213]) by smtp.gmail.com with ESMTPSA id 126-20020aca0684000000b002d417464153sm191671oig.4.2022.02.24.11.16.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Feb 2022 11:16:01 -0800 (PST) Received: (nullmailer pid 3428386 invoked by uid 1000); Thu, 24 Feb 2022 19:16:00 -0000 Date: Thu, 24 Feb 2022 13:16:00 -0600 From: Rob Herring To: Rohit Agarwal Cc: manivannan.sadhasivam@linaro.org, sboyd@kernel.org, robh+dt@kernel.org, agross@kernel.org, mturquette@baylibre.com, linux-clk@vger.kernel.org, bjorn.andersson@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 1/5] dt-bindings: clock: Add A7 PLL binding for SDX65 Message-ID: References: <1645505785-2271-1-git-send-email-quic_rohiagar@quicinc.com> <1645505785-2271-2-git-send-email-quic_rohiagar@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1645505785-2271-2-git-send-email-quic_rohiagar@quicinc.com> X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 22 Feb 2022 10:26:21 +0530, Rohit Agarwal wrote: > Add information for Cortex A7 PLL clock in Qualcomm > platform SDX65. > > Signed-off-by: Rohit Agarwal > --- > Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Acked-by: Rob Herring