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[189.47.54.110]) by smtp.gmail.com with ESMTPSA id w3-20020a056830110300b005af14392276sm79509otq.62.2022.02.24.11.16.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Feb 2022 11:16:40 -0800 (PST) From: Magali Lemes To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@linux.ie, daniel@ffwll.ch Cc: siqueirajordao@riseup.net, mwen@igalia.com, maira.canal@usp.br, isabbasso@riseup.net, Magali Lemes , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] drm/amd/display: Use NULL instead of 0 Date: Thu, 24 Feb 2022 16:15:50 -0300 Message-Id: <20220224191551.69103-4-magalilemes00@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220224191551.69103-1-magalilemes00@gmail.com> References: <20220224191551.69103-1-magalilemes00@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Silence the following sparse warnings: ../drivers/gpu/drm/amd/amdgpu/../display/dc/dce112/dce112_resource.c:865:16: sparse: warning: Using plain integer as NULL pointer ../drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:1588:84: sparse: warning: Using plain integer as NULL pointer ../drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2725:84: sparse: warning: Using plain integer as NULL pointer ../drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_resource.c:1919:16: sparse: warning: Using plain integer as NULL pointer Signed-off-by: Magali Lemes --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 4 +--- 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 4367a6e0c224..cc8e60ec35c6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1924,7 +1924,7 @@ static struct audio *find_first_free_audio( return pool->audios[i]; } } - return 0; + return NULL; } /* diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index ace04e2ed34e..8378b80e8517 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1585,7 +1585,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( hws->funcs.enable_stream_timing(pipe_ctx, context, dc); } - pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; + pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false; @@ -2722,7 +2722,7 @@ static void dce110_program_front_end_for_pipe( pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); - pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; + pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; program_scaler(dc, pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index ee55cda854bf..8104c0c67f78 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -858,11 +858,9 @@ static struct clock_source *find_matching_pll( return pool->clock_sources[DCE112_CLK_SRC_PLL4]; case TRANSMITTER_UNIPHY_F: return pool->clock_sources[DCE112_CLK_SRC_PLL5]; - default: - return NULL; } - return 0; + return NULL; } static enum dc_status build_mapped_resource( -- 2.25.1