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Subject: Re: [PATCH v2 1/2] clk: qcom: clk-rcg2: Update logic to calculate D value for RCG
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     Rajendra Nayak <rnayak@codeaurora.org>,
        linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        Taniya Das <tdas@codeaurora.org>
To:     Michael Turquette <mturquette@baylibre.com>,
        Taniya Das <tdas@codeaurora.org>
Date:   Thu, 24 Feb 2022 14:27:03 -0800
User-Agent: alot/0.10
Message-Id: <20220224222705.C1867C340E9@smtp.kernel.org>
Precedence: bulk

Quoting Taniya Das (2022-02-21 10:13:21)
> The display pixel clock has a requirement on certain newer platforms to
> support M/N as (2/3) and the final D value calculated results in
> underflow errors.
> As the current implementation does not check for D value is within
> the accepted range for a given M & N value. Update the logic to
> calculate the final D value based on the range.
>=20
> Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks")
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---
>  [v2]
>    * Update the if else check with clamp.
>    * Typecast the f->m to u32.
>=20
>  drivers/clk/qcom/clk-rcg2.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
>=20
> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
> index e1b1b426fae4..3a78a2a16cf8 100644
> --- a/drivers/clk/qcom/clk-rcg2.c
> +++ b/drivers/clk/qcom/clk-rcg2.c
> @@ -264,7 +264,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_h=
w *hw,
>=20
>  static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_=
tbl *f)
>  {
> -       u32 cfg, mask;
> +       u32 cfg, mask, d_val, not2d_val, n_minus_m;
>         struct clk_hw *hw =3D &rcg->clkr.hw;
>         int ret, index =3D qcom_find_src_index(hw, rcg->parent_map, f->sr=
c);
>=20
> @@ -283,8 +283,17 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg=
, const struct freq_tbl *f)
>                 if (ret)
>                         return ret;
>=20
> +               /* Calculate 2d value */
> +               d_val =3D f->n;
> +
> +               n_minus_m =3D f->n - f->m;
> +               n_minus_m *=3D 2;
> +
> +               d_val =3D clamp(d_val, (u32)f->m, n_minus_m);

Use clamp_t(u32, d_val, f->m, n_minus_m)

> +               not2d_val =3D ~d_val & mask;
> +
>                 ret =3D regmap_update_bits(rcg->clkr.regmap,
> -                               RCG_D_OFFSET(rcg), mask, ~f->n);
> +                               RCG_D_OFFSET(rcg), mask, not2d_val);
>                 if (ret)