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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g1-20020a1709065d0100b006b9106ceab4si1936810ejt.743.2022.02.25.01.43.11; Fri, 25 Feb 2022 01:43:35 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Dii+kV0O; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238978AbiBYJTc (ORCPT + 99 others); Fri, 25 Feb 2022 04:19:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232671AbiBYJTb (ORCPT ); Fri, 25 Feb 2022 04:19:31 -0500 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3C3E252917; Fri, 25 Feb 2022 01:18:59 -0800 (PST) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 21P9IBjF017495; Fri, 25 Feb 2022 03:18:11 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1645780691; bh=rvWbhCJfnEIOUkIutnw+J3DZO5DRfhnDxkBwC3aC8fE=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=Dii+kV0O8lo7+yx9O7UyWiW3gSP6WIDtP/4eZgE9Ho3Cw26ca86US8X/AxQnfks1G nASL/KcwxckCgSbhpmVeBT9xnbVkTil2IopvLPhBkrOnoL+iOuszuj3r/4TahYOuuD xnFsC8AoW1vpbjkbo3nNFSOHCla7+eB+KnEynj/M= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 21P9IB0H081229 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 25 Feb 2022 03:18:11 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 25 Feb 2022 03:18:10 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 25 Feb 2022 03:18:10 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 21P9IAlO009024; Fri, 25 Feb 2022 03:18:10 -0600 Date: Fri, 25 Feb 2022 14:48:09 +0530 From: Pratyush Yadav To: =?utf-8?Q?C=C3=A9dric?= Le Goater CC: , , Mark Brown , Tudor Ambarus , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , , Joel Stanley , Andrew Jeffery , Chin-Ting Kuo , , Rob Herring , , Subject: Re: [PATCH 08/10] spi: aspeed: Calibrate read timings Message-ID: <20220225091809.gvup3mcst45szi6x@ti.com> References: <20220214094231.3753686-1-clg@kaod.org> <20220214094231.3753686-9-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220214094231.3753686-9-clg@kaod.org> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 14/02/22 10:42AM, C?dric Le Goater wrote: > To accommodate the different response time of SPI transfers on different > boards and different SPI NOR devices, the Aspeed controllers provide a > set of Read Timing Compensation registers to tune the timing delays > depending on the frequency being used. The AST2600 SoC has one of > these registers per device. On the AST2500 and AST2400 SoCs, the > timing register is shared by all devices which is a bit problematic to > get good results other than for one device. > > The algorithm first reads a golden buffer at low speed and then performs > reads with different clocks and delay cycle settings to find a breaking > point. This selects a default good frequency for the CEx control register. > The current settings are bit optimistic as we pick the first delay giving > good results. A safer approach would be to determine an interval and > choose the middle value. > > Due to the lack of API, calibration is performed when the direct mapping > for reads is created. The dirmap_create mapping says nothing about _when_ it should be called. So there is no guarantee that it will only be called after the flash is fully initialized. I suggest you either make this a requirement of the API, or create a new API that guarantees it will only be called after the flash is initialized, like [0]. [0] https://patchwork.ozlabs.org/project/linux-mtd/patch/20210311191216.7363-2-p.yadav@ti.com/ > > Cc: Pratyush Yadav > Signed-off-by: C?dric Le Goater > --- -- Regards, Pratyush Yadav Texas Instruments Inc.