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Date:   Fri, 25 Feb 2022 11:12:20 -0600
From:   Bjorn Helgaas <helgaas@kernel.org>
To:     Pali =?iso-8859-1?Q?Roh=E1r?= <pali@kernel.org>
Cc:     Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Rob Herring <robh+dt@kernel.org>,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
        Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>,
        Marek =?iso-8859-1?Q?Beh=FAn?= <kabel@kernel.org>,
        Russell King <rmk+kernel@armlinux.org.uk>,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 04/12] dt-bindings: PCI: mvebu: Add num-lanes property
Message-ID: <20220225171220.GA364705@bhelgaas>
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On Fri, Feb 25, 2022 at 01:58:10PM +0100, Pali Roh?r wrote:
> On Thursday 24 February 2022 18:02:26 Bjorn Helgaas wrote:
> > On Tue, Feb 22, 2022 at 04:50:22PM +0100, Pali Roh?r wrote:
> > > Controller driver needs to correctly configure PCIe link if it contains 1
> > > or 4 SerDes PCIe lanes. Therefore add a new 'num-lanes' DT property for
> > > mvebu PCIe controller. Property 'num-lanes' seems to be de-facto standard
> > > way how number of lanes is specified in other PCIe controllers.
> > > 
> > > Signed-off-by: Pali Roh?r <pali@kernel.org>
> > > Acked-by: Rob Herring <robh@kernel.org>
> > > ---
> > >  Documentation/devicetree/bindings/pci/mvebu-pci.txt | 11 +++++++++++
> > >  1 file changed, 11 insertions(+)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
> > > index 6173af6885f8..24225852bce0 100644
> > > --- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt
> > > +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
> > > @@ -77,6 +77,7 @@ and the following optional properties:
> > >  - marvell,pcie-lane: the physical PCIe lane number, for ports having
> > >    multiple lanes. If this property is not found, we assume that the
> > >    value is 0.
> > > +- num-lanes: number of SerDes PCIe lanes for this link (1 or 4)
> > >  - reset-gpios: optional GPIO to PERST#
> > >  - reset-delay-us: delay in us to wait after reset de-assertion, if not
> > >    specified will default to 100ms, as required by the PCIe specification.
> > > @@ -141,6 +142,7 @@ pcie-controller {
> > >  		interrupt-map = <0 0 0 0 &mpic 58>;
> > >  		marvell,pcie-port = <0>;
> > >  		marvell,pcie-lane = <0>;
> > > +		num-lanes = <1>;
> > 
> > Is this patch really necessary?
> 
> This is just documentation patch. And I think that documentation is
> always important.
> 
> > AFAICS, the related driver change
> > only sets "port->is_x4 = true" when "num-lanes = <4>", and in all
> > other cases it defaults to a Max Link Width of 1:
> > 
> >   lnkcap |= (port->is_x4 ? 4 : 1) << 4;
> 
> Yes!
> 
> And this registers configures number of lanes in HW.
> 
> > I don't see the point of adding a value that we don't validate or do
> > anything with.  E.g., I don't see an error message that would catch
> > "num-lanes = <3>".
> > 
> > Bjorn
> 
> In past I was told that kernel should not do validation of DT properties
> and it is job of some DT schema validation. That is why I did not added
> code into kernel which show error message when value different than 1
> and 4 is specified in DT.
> 
> But issue here is that there is no DT schema for pci-mvebu as above
> .txt file was not converted to YAML schema yet. This is something which
> should be improved...

I'm OK with this patch as-is, especially since Rob acked it.

Bjorn