Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
MIME-Version: 1.0
References: <20220225145432.422130-1-pgwipeout@gmail.com> <20220225145432.422130-5-pgwipeout@gmail.com>
 <20220225171601.GF13801@jackp-linux.qualcomm.com>
In-Reply-To: <20220225171601.GF13801@jackp-linux.qualcomm.com>
From:   Peter Geis <pgwipeout@gmail.com>
Date:   Fri, 25 Feb 2022 12:55:09 -0500
Message-ID: <CAMdYzYpgECcG55pGFNrNDmhGZuuY19VOBK4uBZQQ0JSc0xu+1Q@mail.gmail.com>
Subject: Re: [PATCH v1 4/8] usb: dwc3: core: do not use 3.0 clock when
 operating in 2.0 mode
To:     Jack Pham <quic_jackp@quicinc.com>
Cc:     Felipe Balbi <balbi@kernel.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Bin Yang <yangbin@rock-chips.com>,
        Heiko Stuebner <heiko@sntech.de>, linux-usb@vger.kernel.org,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

On Fri, Feb 25, 2022 at 12:16 PM Jack Pham <quic_jackp@quicinc.com> wrote:
>
> +Thinh
>
> Hi Peter,
>
> On Fri, Feb 25, 2022 at 09:54:27AM -0500, Peter Geis wrote:
> > From: Bin Yang <yangbin@rock-chips.com>
> >
> > In the 3.0 device core, if the core is programmed to operate in
> > 2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
> > the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
> > clock. Enabling this feature allows the pipe3 clock to be not-running
> > when forcibly operating in 2.0 device mode.
> >
> > Signed-off-by: Bin Yang <yangbin@rock-chips.com>
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> >  drivers/usb/dwc3/core.c | 4 ++++
> >  drivers/usb/dwc3/core.h | 1 +
> >  2 files changed, 5 insertions(+)
> >
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > index 18adddfba3da..032d40794fae 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -1167,6 +1167,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
> >               if (dwc->parkmode_disable_ss_quirk)
> >                       reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
> >
> > +             if (dwc->maximum_speed == USB_SPEED_HIGH ||
> > +                 dwc->maximum_speed == USB_SPEED_FULL)
> > +                     reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
> > +
>
> I doubt this is applicable to all revisions of the DWC_usb3x IP cores?
> For instance in the programming guide for DWC_usb31 1.90a bit 26 of
> GUCTL1 is 'Reserved'.  While I do see it in the DWC_usb3 databook,
> table 4-8 entry "Remove pipe_clk mux for 2.0 mode?" mentions this
> feature was only added in v2.90a.

I was wondering about that, thanks for confirming for me.
Is it possible to get a copy of this programming guide or is it closed?

>
> So this setting at least needs a revision check to make sure we're not
> causing unexpected behavior.  Something like
>
>         DWC3_VER_IS_WITHIN(DWC3, 290A, ANY)

Will do, I appreciate it.

>
> Jack
>
> >               dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
> >       }
> >
> > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> > index eb9c1efced05..ea3ca04406bb 100644
> > --- a/drivers/usb/dwc3/core.h
> > +++ b/drivers/usb/dwc3/core.h
> > @@ -259,6 +259,7 @@
> >  /* Global User Control 1 Register */
> >  #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT    BIT(31)
> >  #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS   BIT(28)
> > +#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK      BIT(26)
> >  #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW                BIT(24)
> >  #define DWC3_GUCTL1_PARKMODE_DISABLE_SS              BIT(17)
> >
> > --
> > 2.25.1
> >