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Date:   Fri, 25 Feb 2022 15:38:05 -0500
From:   =?utf-8?B?TsOtY29sYXMgRi4gUi4gQS4=?= Prado 
        <nfraprado@collabora.com>
To:     Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Cc:     Matthias Brugger <matthias.bgg@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        --to=Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
        Project_Global_Chrome_Upstream_Group@mediatek.com,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
        Chen-Yu Tsai <wenst@chromium.org>,
        Ryder Lee <ryder.lee@kernel.org>
Subject: Re: [PATCH v2 14/23] arm64: dts: mt8192: Add mipi_tx node
Message-ID: <20220225203805.xv3sxwi6ucfp6zdq@notapiano>
References: <20220218091633.9368-1-allen-kh.cheng@mediatek.com>
 <20220218091633.9368-15-allen-kh.cheng@mediatek.com>
 <20220222212658.xuau6t3xcvu7m4uz@notapiano>
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On Tue, Feb 22, 2022 at 04:27:03PM -0500, N?colas F. R. A. Prado wrote:
> On Fri, Feb 18, 2022 at 05:16:24PM +0800, Allen-KH Cheng wrote:
> > Add mipi_tx node for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index cfc2db501108..f5e5af949f19 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1114,6 +1114,16 @@
> >  			};
> >  		};
> >  
> > +		mipi_tx0: mipi-dphy@11e50000 {
> 
> According to Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml, this
> node's name should be dsi-phy, not mipi-dphy.
> 
> > +			compatible = "mediatek,mt8183-mipi-tx";
> > +			reg = <0 0x11e50000 0 0x1000>;
> > +			clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> > +			clock-names = "ref_clk";

Also, this clock-names should be dropped [1].

[1] https://lore.kernel.org/all/CAAOTY_84OF71QK6M5JT1M5YAFKED_xWVpx8B8t859OsVxE0cfQ@mail.gmail.com/

> > +			#clock-cells = <0>;
> > +			#phy-cells = <0>;
> > +			clock-output-names = "mipi_tx0_pll";
> > +		};
> > +
> >  		i2c0: i2c@11f00000 {
> >  			compatible = "mediatek,mt8192-i2c";
> >  			reg = <0 0x11f00000 0 0x1000>,
> > -- 
> > 2.18.0
> > 
> >