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To:     Marc Zyngier <maz@kernel.org>
Cc:     Thomas Gleixner <tglx@linutronix.de>,
        Rob Herring <robh+dt@kernel.org>,
        Sven Peter <sven@svenpeter.dev>,
        Alyssa Rosenzweig <alyssa@rosenzweig.io>,
        Mark Kettenis <mark.kettenis@xs4all.nl>,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org
References: <20220224130741.63924-1-marcan@marcan.st>
 <20220224130741.63924-4-marcan@marcan.st> <87mtif2eoz.wl-maz@kernel.org>
From:   Hector Martin <marcan@marcan.st>
Subject: Re: [PATCH v2 3/7] irqchip/apple-aic: Add Fast IPI support
Message-ID: <d0e2a08e-79d6-03e8-09a2-bb634fa3c23c@marcan.st>
Date:   Mon, 28 Feb 2022 00:33:54 +0900
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On 25/02/2022 23.39, Marc Zyngier wrote:
> On Thu, 24 Feb 2022 13:07:37 +0000,
>>  		if (!(pending & irq_bit) &&
>> -		    (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit))
>> -			send |= AIC_IPI_SEND_CPU(cpu);
>> +		    (atomic_read(per_cpu_ptr(&aic_vipi_enable, cpu)) & irq_bit)) {
>> +			if (static_branch_likely(&use_fast_ipi))
>> +				aic_ipi_send_fast(cpu);
> 
> OK, this is suffering from the same issue that GICv3 has, which is
> that memory barriers don't provide order against sysregs. You need a
> DSB for that, which is a pain. Something like this:

Doesn't the control flow here guarantee the ordering? atomic_read() must
complete before the sysreg is written since there is a control flow
dependency, and the prior atomic/barrier dance ensures that read is
ordered properly with everything that comes before it.

-- 
Hector Martin (marcan@marcan.st)
Public Key: https://mrcn.st/pub