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From:   Peng Fan <peng.fan@nxp.com>
To:     Abel Vesa <abel.vesa@nxp.com>,
        "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
CC:     "sboyd@kernel.org" <sboyd@kernel.org>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>,
        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>,
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        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 3/3] clk: imx8mp: remove SYS PLL 1/2 clock gates
Thread-Topic: [PATCH 3/3] clk: imx8mp: remove SYS PLL 1/2 clock gates
Thread-Index: AQHYKh/pjVRxh52TuUCry9PuZTCQ2qykVYuAgAPL2kA=
Date:   Mon, 28 Feb 2022 00:39:45 +0000
Message-ID: <DU0PR04MB9417D1BF8C068E5636C60F9E88019@DU0PR04MB9417.eurprd04.prod.outlook.com>
References: <20220225081733.2294166-1-peng.fan@oss.nxp.com>
 <20220225081733.2294166-4-peng.fan@oss.nxp.com> <YhjpIbIVf7DQh/Ja@abelvesa>
In-Reply-To: <YhjpIbIVf7DQh/Ja@abelvesa>
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Hi Abel,

> Subject: Re: [PATCH 3/3] clk: imx8mp: remove SYS PLL 1/2 clock gates
>=20
> On 22-02-25 16:17:33, Peng Fan (OSS) wrote:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > Remove the PLL 1/2 gates as it make AMP clock management harder
> > without obvious benifit.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  drivers/clk/imx/clk-imx8mp.c | 48
> > ++++++++++++------------------------
> >  1 file changed, 16 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx8mp.c
> > b/drivers/clk/imx/clk-imx8mp.c index f23b92906d3b..18f5b7c3ca9d
> 100644
> > --- a/drivers/clk/imx/clk-imx8mp.c
> > +++ b/drivers/clk/imx/clk-imx8mp.c
> > @@ -480,44 +480,28 @@ static int imx8mp_clocks_probe(struct
> platform_device *pdev)
> >  	hws[IMX8MP_ARM_PLL_OUT] =3D imx_clk_hw_gate("arm_pll_out",
> "arm_pll_bypass", anatop_base + 0x84, 11);
> >  	hws[IMX8MP_SYS_PLL3_OUT] =3D imx_clk_hw_gate("sys_pll3_out",
> > "sys_pll3_bypass", anatop_base + 0x114, 11);
> >
> > -	hws[IMX8MP_SYS_PLL1_40M_CG] =3D
> imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1_bypass", anatop_base + 0x94,
> 27);
>=20
> Hmm, isn't there a chance that u-boot might gate these? Then, in kernel y=
ou
> won't have a way to ungate them, leaving the consumers hanging.

Both NXP and Upstream U-Boot not touch these bits. With the CG managed
by Linux, it is hard to support AMP. This is same to Lucas's patch to
clk-imx8mq.c to drop the gate.

The other method to support AMP well, is to add the CGs clk in device tree =
node
for Mcore. But we still need a method to support M core booted in U-Boot, a=
nd
linux may gate off the clock.

Thanks,
Peng.

>=20
> > -	hws[IMX8MP_SYS_PLL1_80M_CG] =3D
> imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1_bypass", anatop_base + 0x94,
> 25);
> > -	hws[IMX8MP_SYS_PLL1_100M_CG] =3D
> imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1_bypass", anatop_base +
> 0x94, 23);
> > -	hws[IMX8MP_SYS_PLL1_133M_CG] =3D
> imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1_bypass", anatop_base +
> 0x94, 21);
> > -	hws[IMX8MP_SYS_PLL1_160M_CG] =3D
> imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1_bypass", anatop_base +
> 0x94, 19);
> > -	hws[IMX8MP_SYS_PLL1_200M_CG] =3D
> imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1_bypass", anatop_base +
> 0x94, 17);
> > -	hws[IMX8MP_SYS_PLL1_266M_CG] =3D
> imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1_bypass", anatop_base +
> 0x94, 15);
> > -	hws[IMX8MP_SYS_PLL1_400M_CG] =3D
> imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1_bypass", anatop_base +
> 0x94, 13);
> >  	hws[IMX8MP_SYS_PLL1_OUT] =3D imx_clk_hw_gate("sys_pll1_out",
> > "sys_pll1_bypass", anatop_base + 0x94, 11);
> >
> > -	hws[IMX8MP_SYS_PLL1_40M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20);
> > -	hws[IMX8MP_SYS_PLL1_80M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10);
> > -	hws[IMX8MP_SYS_PLL1_100M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8);
> > -	hws[IMX8MP_SYS_PLL1_133M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6);
> > -	hws[IMX8MP_SYS_PLL1_160M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5);
> > -	hws[IMX8MP_SYS_PLL1_200M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4);
> > -	hws[IMX8MP_SYS_PLL1_266M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3);
> > -	hws[IMX8MP_SYS_PLL1_400M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2);
> > +	hws[IMX8MP_SYS_PLL1_40M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
> > +	hws[IMX8MP_SYS_PLL1_80M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
> > +	hws[IMX8MP_SYS_PLL1_100M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
> > +	hws[IMX8MP_SYS_PLL1_133M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
> > +	hws[IMX8MP_SYS_PLL1_160M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
> > +	hws[IMX8MP_SYS_PLL1_200M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
> > +	hws[IMX8MP_SYS_PLL1_266M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
> > +	hws[IMX8MP_SYS_PLL1_400M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_400m",
> > +"sys_pll1_out", 1, 2);
> >  	hws[IMX8MP_SYS_PLL1_800M] =3D
> imx_clk_hw_fixed_factor("sys_pll1_800m",
> > "sys_pll1_out", 1, 1);
> >
> > -	hws[IMX8MP_SYS_PLL2_50M_CG] =3D
> imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2_bypass", anatop_base +
> 0x104, 27);
> > -	hws[IMX8MP_SYS_PLL2_100M_CG] =3D
> imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2_bypass", anatop_base +
> 0x104, 25);
> > -	hws[IMX8MP_SYS_PLL2_125M_CG] =3D
> imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2_bypass", anatop_base +
> 0x104, 23);
> > -	hws[IMX8MP_SYS_PLL2_166M_CG] =3D
> imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2_bypass", anatop_base +
> 0x104, 21);
> > -	hws[IMX8MP_SYS_PLL2_200M_CG] =3D
> imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2_bypass", anatop_base +
> 0x104, 19);
> > -	hws[IMX8MP_SYS_PLL2_250M_CG] =3D
> imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2_bypass", anatop_base +
> 0x104, 17);
> > -	hws[IMX8MP_SYS_PLL2_333M_CG] =3D
> imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2_bypass", anatop_base +
> 0x104, 15);
> > -	hws[IMX8MP_SYS_PLL2_500M_CG] =3D
> imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2_bypass", anatop_base +
> 0x104, 13);
> >  	hws[IMX8MP_SYS_PLL2_OUT] =3D imx_clk_hw_gate("sys_pll2_out",
> > "sys_pll2_bypass", anatop_base + 0x104, 11);
> >
> > -	hws[IMX8MP_SYS_PLL2_50M] =3D
> imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20);
> > -	hws[IMX8MP_SYS_PLL2_100M] =3D
> imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10);
> > -	hws[IMX8MP_SYS_PLL2_125M] =3D
> imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
> > -	hws[IMX8MP_SYS_PLL2_166M] =3D
> imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
> > -	hws[IMX8MP_SYS_PLL2_200M] =3D
> imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
> > -	hws[IMX8MP_SYS_PLL2_250M] =3D
> imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
> > -	hws[IMX8MP_SYS_PLL2_333M] =3D
> imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
> > -	hws[IMX8MP_SYS_PLL2_500M] =3D
> imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
> > +	hws[IMX8MP_SYS_PLL2_50M] =3D
> imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
> > +	hws[IMX8MP_SYS_PLL2_100M] =3D
> imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
> > +	hws[IMX8MP_SYS_PLL2_125M] =3D
> imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
> > +	hws[IMX8MP_SYS_PLL2_166M] =3D
> imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
> > +	hws[IMX8MP_SYS_PLL2_200M] =3D
> imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
> > +	hws[IMX8MP_SYS_PLL2_250M] =3D
> imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
> > +	hws[IMX8MP_SYS_PLL2_333M] =3D
> imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
> > +	hws[IMX8MP_SYS_PLL2_500M] =3D
> imx_clk_hw_fixed_factor("sys_pll2_500m",
> > +"sys_pll2_out", 1, 2);
> >  	hws[IMX8MP_SYS_PLL2_1000M] =3D
> > imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
> >
> >  	hws[IMX8MP_CLK_A53_DIV] =3D
> imx8m_clk_hw_composite_core("arm_a53_div",
> > imx8mp_a53_sels, ccm_base + 0x8000);
> > --
> > 2.25.1
> >