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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a2ff4d42-19ba-4e50-0fca-08d9fa5384ac X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Feb 2022 00:44:46.4109 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ZJh+l2IfiP6Q0neHcfUPUwKdNALOKNEpzUZN3b3U7RJOo5MkJdFTsMeuOb9d3wuPpQuvmTEXDYi1UkhuB9FbCA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB8675 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Rob, > Subject: Re: [PATCH] dt-bindings: serial: fsl-lpuart: Add imx93 compatibl= e > string >=20 > On Tue, Feb 15, 2022 at 04:13:34PM +0800, Peng Fan (OSS) wrote: > > From: Peng Fan > > > > The lpuart on i.MX93 is derived from i.MX8ULP with some industrial > > enhancements, it uses three compatible strings, so update the >=20 > Looks like it's 2 compatible strings... Oh, yes. i.MX8ULP/7ULP is same uart IP. >=20 > > compatible string for i.MX93. But for a few instants, >=20 > s/instants/instances/ >=20 > > DTR_B, DSR_B, DCD_B and RIN_B pins are supported, so use one > > compatible string fsl,imx93-lpuart-v2 >=20 > If the differences are just what gets pinned out, then I think the differ= ences > should be handled with separate properties. We probably already have some= . >=20 > Plus, while you may have all the above signals, a board design may still = only > use a subset. It is SoC integration level with above features not support in some instanc= es, so no such signals connected to SoC pin. Saying LPUART IP itself support DTR/DSR/DCD/RIN, but instance A has the feature disabled when doing SoC integration, instance B has the feature ena= bled when doing SoC integration. What's your suggestion with such case? Thanks, Peng. >=20 > > > > Signed-off-by: Peng Fan > > --- > > Documentation/devicetree/bindings/serial/fsl-lpuart.yaml | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml > > b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml > > index 6e04e3848261..d7805f31ccc2 100644 > > --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml > > +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml > > @@ -24,6 +24,8 @@ properties: > > - fsl,imxrt1050-lpuart > > - items: > > - enum: > > + - fsl,imx93-lpuart > > + - fsl,imx93-lpuart-v2 > > - fsl,imx8qxp-lpuart > > - fsl,imx8ulp-lpuart > > - const: fsl,imx7ulp-lpuart > > -- > > 2.25.1 > > > >