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Date:   Mon, 28 Feb 2022 10:54:03 +0100
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Subject: Re: [PATCH v1] arm/arm64: dts: mediatek: Format mediatek,larbs as an
 array of phandles
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To:     =?UTF-8?B?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= 
        <nfraprado@collabora.com>
Cc:     kernel@collabora.com, Rob Herring <robh+dt@kernel.org>,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org
References: <20220225225315.80220-1-nfraprado@collabora.com>
From:   Matthias Brugger <matthias.bgg@gmail.com>
In-Reply-To: <20220225225315.80220-1-nfraprado@collabora.com>
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Hi Nícolas,

On 25/02/2022 23:53, Nícolas F. R. A. Prado wrote:
> Commit 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas")
> updated the mediatek,larbs property in the mediatek,iommu.yaml
> dt-binding to make it clearer that the phandles passed to the property
> are independent, rather than subsequent arguments to the first phandle.
> 
> Update the mediatek,larbs property in the Devicetrees to use the same
> formatting. This change doesn't impact any behavior: the compiled dtb is
> exactly the same. It does however fix the warnings generated by
> dtbs_check.
> 
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> 
> ---
> 
>   arch/arm/boot/dts/mt2701.dtsi             | 2 +-
>   arch/arm/boot/dts/mt7623n.dtsi            | 2 +-

Thanks for your patch. Would you mind to split it in two parts. One for 64 bit 
and one 32 bits?

Regards,
Matthias

>   arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 6 +++---
>   arch/arm64/boot/dts/mediatek/mt8167.dtsi  | 2 +-
>   arch/arm64/boot/dts/mediatek/mt8173.dtsi  | 4 ++--
>   arch/arm64/boot/dts/mediatek/mt8183.dtsi  | 4 ++--
>   6 files changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 4776f85d6d5b..64722285228c 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -222,7 +222,7 @@ iommu: mmsys_iommu@10205000 {
>   		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
>   		clocks = <&infracfg CLK_INFRA_M4U>;
>   		clock-names = "bclk";
> -		mediatek,larbs = <&larb0 &larb1 &larb2>;
> +		mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
>   		#iommu-cells = <1>;
>   	};
>   
> diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mt7623n.dtsi
> index bcb0846e29fd..f9e031621c80 100644
> --- a/arch/arm/boot/dts/mt7623n.dtsi
> +++ b/arch/arm/boot/dts/mt7623n.dtsi
> @@ -107,7 +107,7 @@ iommu: mmsys_iommu@10205000 {
>   		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
>   		clocks = <&infracfg CLK_INFRA_M4U>;
>   		clock-names = "bclk";
> -		mediatek,larbs = <&larb0 &larb1 &larb2>;
> +		mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
>   		#iommu-cells = <1>;
>   	};
>   
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> index de16c0d80c30..973c9beade0c 100644
> --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> @@ -329,8 +329,8 @@ iommu0: iommu@10205000 {
>   		interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
>   		clocks = <&infracfg CLK_INFRA_M4U>;
>   		clock-names = "bclk";
> -		mediatek,larbs = <&larb0 &larb1 &larb2
> -				  &larb3 &larb6>;
> +		mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
> +				 <&larb3>, <&larb6>;
>   		#iommu-cells = <1>;
>   	};
>   
> @@ -346,7 +346,7 @@ iommu1: iommu@1020a000 {
>   		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
>   		clocks = <&infracfg CLK_INFRA_M4U>;
>   		clock-names = "bclk";
> -		mediatek,larbs = <&larb4 &larb5 &larb7>;
> +		mediatek,larbs = <&larb4>, <&larb5>, <&larb7>;
>   		#iommu-cells = <1>;
>   	};
>   
> diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> index 9029051624a6..54655f2feb04 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> @@ -174,7 +174,7 @@ larb2: larb@16010000 {
>   		iommu: m4u@10203000 {
>   			compatible = "mediatek,mt8167-m4u";
>   			reg = <0 0x10203000 0 0x1000>;
> -			mediatek,larbs = <&larb0 &larb1 &larb2>;
> +			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
>   			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
>   			#iommu-cells = <1>;
>   		};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 2b7d331a4588..042feaedda4a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -588,8 +588,8 @@ iommu: iommu@10205000 {
>   			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
>   			clocks = <&infracfg CLK_INFRA_M4U>;
>   			clock-names = "bclk";
> -			mediatek,larbs = <&larb0 &larb1 &larb2
> -					  &larb3 &larb4 &larb5>;
> +			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
> +					 <&larb3>, <&larb4>, <&larb5>;
>   			#iommu-cells = <1>;
>   		};
>   
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 00f2ddd245e1..523741150968 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -682,8 +682,8 @@ iommu: iommu@10205000 {
>   			compatible = "mediatek,mt8183-m4u";
>   			reg = <0 0x10205000 0 0x1000>;
>   			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
> -			mediatek,larbs = <&larb0 &larb1 &larb2 &larb3
> -					  &larb4 &larb5 &larb6>;
> +			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>,
> +					 <&larb4>, <&larb5>, <&larb6>;
>   			#iommu-cells = <1>;
>   		};
>