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From:   "Wu, Hao" <hao.wu@intel.com>
To:     "Zhang, Tianfei" <tianfei.zhang@intel.com>,
        "trix@redhat.com" <trix@redhat.com>,
        "mdf@kernel.org" <mdf@kernel.org>,
        "Xu, Yilun" <yilun.xu@intel.com>,
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        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
CC:     "corbet@lwn.net" <corbet@lwn.net>
Subject: RE: [PATCH v1] fpga: dfl: check feature type before parse irq info
Thread-Topic: [PATCH v1] fpga: dfl: check feature type before parse irq info
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Date:   Mon, 28 Feb 2022 11:09:58 +0000
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References: <20220224092242.127081-1-tianfei.zhang@intel.com>
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> Subject: [PATCH v1] fpga: dfl: check feature type before parse irq info
>=20
> From: Tianfei Zhang <tianfei.zhang@intel.com>
>=20
> The feature ID of "Port User Interrupt" and the
> "PMCI Subsystem" are identical, 0x12, but one is for FME,
> other is for Port. It should check the feature type While
> parsing the irq info in parse_feature_irqs().
>=20
> Fixes: 8d021039cbb5 ("fpga: dfl: parse interrupt info for feature devices=
 on
> enumeration")

Actually this is not a real bug, as in original design, there is no overlap=
 for FME and
Port features. This is why you see features for Port doesn't start from 0. =
But anyway
I am good with such extension.

> Link: https://lore.kernel.org/linux-
> fpga/BN9PR11MB54833D7636348D62F931526CE33A9@BN9PR11MB5483.nam
> prd11.prod.outlook.com/
>=20
> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
> ---
>  Documentation/fpga/dfl.rst |  5 +++++
>  drivers/fpga/dfl.c         | 38 ++++++++++++++++++++++----------------
>  2 files changed, 27 insertions(+), 16 deletions(-)
>=20
> diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
> index ef9eec71f6f3..9ce418da1876 100644
> --- a/Documentation/fpga/dfl.rst
> +++ b/Documentation/fpga/dfl.rst
> @@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver
> with matched feature id.
>  FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme=
-pr.c)
>  could be a reference.
>=20
> +Individual DFL drivers are bound DFL devices based on Feature Type and
> Feature ID.
> +The definition of Feature Type and Feature ID can be found:
> +
> +https://github.com/OPAE/linux-dfl-feature-id/blob/master/dfl-feature-ids=
.rst

Thanks for tracking ID allocations. could we also add some description that=
 if
user want to implement a new private feature, then they need to submit new
ID application to https://github.com/OPAE/linux-dfl-feature-id, and add som=
e
README file to guide people for the application process?

Thanks
Hao

> +
>  Location of DFLs on a PCI Device
>  =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D
>  The original method for finding a DFL on a PCI device assumed the start =
of the
> diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
> index 599bb21d86af..6bff39ff21a0 100644
> --- a/drivers/fpga/dfl.c
> +++ b/drivers/fpga/dfl.c
> @@ -940,9 +940,12 @@ static int parse_feature_irqs(struct
> build_feature_devs_info *binfo,
>  {
>  	void __iomem *base =3D binfo->ioaddr + ofst;
>  	unsigned int i, ibase, inr =3D 0;
> +	enum dfl_id_type type;
>  	int virq;
>  	u64 v;
>=20
> +	type =3D feature_dev_id_type(binfo->feature_dev);
> +
>  	/*
>  	 * Ideally DFL framework should only read info from DFL header, but
>  	 * current version DFL only provides mmio resources information for
> @@ -957,22 +960,25 @@ static int parse_feature_irqs(struct
> build_feature_devs_info *binfo,
>  	 * code will be added. But in order to be compatible to old version
>  	 * DFL, the driver may still fall back to these quirks.
>  	 */
> -	switch (fid) {
> -	case PORT_FEATURE_ID_UINT:
> -		v =3D readq(base + PORT_UINT_CAP);
> -		ibase =3D FIELD_GET(PORT_UINT_CAP_FST_VECT, v);
> -		inr =3D FIELD_GET(PORT_UINT_CAP_INT_NUM, v);
> -		break;
> -	case PORT_FEATURE_ID_ERROR:
> -		v =3D readq(base + PORT_ERROR_CAP);
> -		ibase =3D FIELD_GET(PORT_ERROR_CAP_INT_VECT, v);
> -		inr =3D FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v);
> -		break;
> -	case FME_FEATURE_ID_GLOBAL_ERR:
> -		v =3D readq(base + FME_ERROR_CAP);
> -		ibase =3D FIELD_GET(FME_ERROR_CAP_INT_VECT, v);
> -		inr =3D FIELD_GET(FME_ERROR_CAP_SUPP_INT, v);
> -		break;
> +	if (type =3D=3D PORT_ID) {
> +		switch (fid) {
> +		case PORT_FEATURE_ID_UINT:
> +			v =3D readq(base + PORT_UINT_CAP);
> +			ibase =3D FIELD_GET(PORT_UINT_CAP_FST_VECT, v);
> +			inr =3D FIELD_GET(PORT_UINT_CAP_INT_NUM, v);
> +			break;
> +		case PORT_FEATURE_ID_ERROR:
> +			v =3D readq(base + PORT_ERROR_CAP);
> +			ibase =3D FIELD_GET(PORT_ERROR_CAP_INT_VECT, v);
> +			inr =3D FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v);
> +			break;
> +		}
> +	} else if (type =3D=3D FME_ID) {
> +		if (fid =3D=3D FME_FEATURE_ID_GLOBAL_ERR) {
> +			v =3D readq(base + FME_ERROR_CAP);
> +			ibase =3D FIELD_GET(FME_ERROR_CAP_INT_VECT, v);
> +			inr =3D FIELD_GET(FME_ERROR_CAP_SUPP_INT, v);
> +		}
>  	}
>=20
>  	if (!inr) {
> --
> 2.26.2