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References: <20220216052110.1053665-1-mchitale@ventanamicro.com> <20220216052110.1053665-2-mchitale@ventanamicro.com>
In-Reply-To: <20220216052110.1053665-2-mchitale@ventanamicro.com>
From:   Anup Patel <anup@brainfault.org>
Date:   Mon, 28 Feb 2022 18:39:44 +0530
Message-ID: <CAAhSdy2imgdYY8nv30Z_Am1PmR83uBy041H07N2+YivnRJN1kg@mail.gmail.com>
Subject: Re: [RFC PATCH 1/2] riscv: enum for svinval extension
To:     Mayuresh Chitale <mchitale@ventanamicro.com>
Cc:     Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Atish Patra <atishp@rivosinc.com>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>
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On Wed, Feb 16, 2022 at 10:51 AM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> Similar to the other ISA extensions, this patch enables
> callers to check for the presence for the svinval extension.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>

Please update riscv_fill_hwcap() in arch/riscv/kernel/cpufeature.c
to probe Svinval extension.

Regards,
Anup

> ---
>  arch/riscv/include/asm/hwcap.h | 1 +
>  arch/riscv/kernel/cpu.c        | 1 +
>  2 files changed, 2 insertions(+)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 691fc9c8099b..bbff7cb279ea 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -51,6 +51,7 @@ extern unsigned long elf_hwcap;
>   * available logical extension id.
>   */
>  enum riscv_isa_ext_id {
> +       RISCV_ISA_EXT_SVINVAL = RISCV_ISA_EXT_BASE,
>         RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
>  };
>
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index ced7e5be8641..ff0613f8cc39 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -71,6 +71,7 @@ int riscv_of_parent_hartid(struct device_node *node)
>         }
>
>  static struct riscv_isa_ext_data isa_ext_arr[] = {
> +       __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
>         __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
>  };
>
> --
> 2.25.1
>