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[2620:137:e000::1:20]) by mx.google.com with ESMTP id qa6-20020a170907868600b006d1aa558fa8si9390306ejc.872.2022.02.28.09.46.15; Mon, 28 Feb 2022 09:46:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=hE+Pxhcy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237974AbiB1Qrn (ORCPT + 99 others); Mon, 28 Feb 2022 11:47:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236321AbiB1Qrm (ORCPT ); Mon, 28 Feb 2022 11:47:42 -0500 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE99C83038 for ; Mon, 28 Feb 2022 08:47:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646066823; x=1677602823; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=d1WgYu4v5V8Z7rVxe9pdwk9MSrnrrOz1ni41OvnRn8Y=; b=hE+PxhcyovZKgurPoCFywPQ9IjwRKEQ3BJZMzVC9vz2gptm0cOtM0YQ5 WJ/3d1pkD3bMrg0lhjnWBTBQj5RvS+Fg6kOn0xGLOBffgEztGyI9plE+v f0hGXEDKK88W7Kpg6j2Dkf/dH+iUWabMvGpNwydrkGe4wr8kVKQkDEwdc oOrkno28R1UpAn8FPQpDHy2rMOktpA+zQpvfmN54VTtfHy1vGOsL0K2ml PTjhhhkp/vn+0v4oMKpMkdl7wyLwQIuiaP/7B0j2fq255DEiDLy5KP/H2 XVaKUw+xhgnwRTHJuaZsrhQbTlJwmBIDe0OQ0Y4cSjndtWta06VZbGJGt g==; X-IronPort-AV: E=McAfee;i="6200,9189,10272"; a="313644055" X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="313644055" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 08:47:03 -0800 X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="550312451" Received: from eliasbro-mobl.amr.corp.intel.com (HELO [10.212.174.65]) ([10.212.174.65]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 08:47:02 -0800 Message-ID: Date: Mon, 28 Feb 2022 08:46:57 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCHv4 29/30] ACPICA: Avoid cache flush on TDX guest Content-Language: en-US To: "Kirill A. Shutemov" , Dan Williams Cc: Josh Poimboeuf , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Andy Lutomirski , Peter Zijlstra , Kuppuswamy Sathyanarayanan , Andrea Arcangeli , Andi Kleen , David Hildenbrand , "H. Peter Anvin" , Juergen Gross , Jim Mattson , Joerg Roedel , Kuppuswamy Sathyanarayanan , Paolo Bonzini , sdeep@vmware.com, Sean Christopherson , "Luck, Tony" , Vitaly Kuznetsov , Wanpeng Li , Tom Lendacky , Brijesh Singh , X86 ML , Linux Kernel Mailing List References: <20220224155630.52734-1-kirill.shutemov@linux.intel.com> <20220224155630.52734-30-kirill.shutemov@linux.intel.com> <20220227220526.3rrmy3u7j2xpelcn@treble> <20220228163713.5eewdwcqhmulsp4z@black.fi.intel.com> From: Dave Hansen In-Reply-To: <20220228163713.5eewdwcqhmulsp4z@black.fi.intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A, RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2/28/22 08:37, Kirill A. Shutemov wrote: >> Agree, why is this marked as "TODO"? The cache flushes associated with >> ACPI sleep states are to flush cache before bare metal power loss to >> CPU caches and bare metal transition of DDR in self-refresh mode. If a >> cache flush is required it is the responsibility of the hypervisor. >> Either it is safe for all guests or it is unsafe for all guests, not >> TD specific. > Do we have "any VM" check? I can't find it right away. Yes: > #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */ I'm pretty sure an earlier version of this patch used it.