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[209.85.221.42]) by smtp.gmail.com with ESMTPSA id y12-20020a50eb8c000000b00410f02e577esm6849368edr.7.2022.02.28.17.10.24 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Feb 2022 17:10:25 -0800 (PST) Received: by mail-wr1-f42.google.com with SMTP id i8so964177wrr.8 for ; Mon, 28 Feb 2022 17:10:24 -0800 (PST) X-Received: by 2002:a5d:62cb:0:b0:1ef:5d3f:7b56 with SMTP id o11-20020a5d62cb000000b001ef5d3f7b56mr14343243wrv.513.1646097024460; Mon, 28 Feb 2022 17:10:24 -0800 (PST) MIME-Version: 1.0 References: <1644591438-6514-1-git-send-email-quic_srivasam@quicinc.com> <1644591438-6514-3-git-send-email-quic_srivasam@quicinc.com> In-Reply-To: <1644591438-6514-3-git-send-email-quic_srivasam@quicinc.com> From: Doug Anderson Date: Mon, 28 Feb 2022 17:10:12 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 2/3] arm64: dts: qcom: sc7280: Add lpass cpu node To: Srinivasa Rao Mandadapu Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , Rohit kumar , Srinivas Kandagatla , Stephen Boyd , Judy Hsiao , Venkata Prasad Potturu Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Fri, Feb 11, 2022 at 6:57 AM Srinivasa Rao Mandadapu wrote: > > @@ -1750,6 +1751,64 @@ > #clock-cells = <1>; > }; > > + lpass_cpu: audio-subsystem@3260000 { > + compatible = "qcom,sc7280-lpass-cpu"; > + reg = <0 0x3260000 0 0xC000>, > + <0 0x3280000 0 0x29000>, > + <0 0x3340000 0 0x29000>, > + <0 0x336C000 0 0x3000>, > + <0 0x3987000 0 0x68000>, > + <0 0x3B00000 0 0x29000>; Lower case hex, please. ...and pad the address to 8 digits here (just don't do it in the unit address in the node name). > + reg-names = "lpass-rxtx-cdc-dma-lpm", > + "lpass-rxtx-lpaif", > + "lpass-va-lpaif", > + "lpass-va-cdc-dma-lpm", > + "lpass-hdmiif", > + "lpass-lpaif"; The order of "reg" and "reg-names" needs to match the bindings exactly. It's almost certainly easier to change your device tree since the bindings have already landed. That means that "lpass-hdmiif" will be first. ...and it will also change your node name since the first "reg" listed will now be 3987000. > + iommus = <&apps_smmu 0x1820 0>, > + <&apps_smmu 0x1821 0>, > + <&apps_smmu 0x1832 0>; > + status = "disabled"; > + > + power-domains = <&rpmhpd SC7280_LCX>; > + power-domain-names = "lcx"; power-domain-names is not in the bindings. > + required-opps = <&rpmhpd_opp_nom>; > + > + clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, > + <&lpasscore LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, > + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, > + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, > + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, > + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, > + <&lpasscore LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, > + <&lpasscore LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, > + <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; > + clock-names = "aon_cc_audio_hm_h", > + "core_cc_sysnoc_mport_core", > + "audio_cc_codec_mem", > + "audio_cc_codec_mem0", > + "audio_cc_codec_mem1", > + "audio_cc_codec_mem2", > + "core_cc_ext_if0_ibit", > + "core_cc_ext_if1_ibit", > + "aon_cc_va_mem0"; Clocks do not match bindings. > + #sound-dai-cells = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + interrupts = , > + , > + , > + ; > + > + interrupt-names = "lpass-irq-lpaif", > + "lpass-irq-vaif", > + "lpass-irq-rxtxif", > + "lpass-irq-hdmi"; interrupt-names ordering does not match bindings. -Doug