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[2620:137:e000::1:20]) by mx.google.com with ESMTP id x2-20020a170902ea8200b0015005f29be7si11506580plb.84.2022.03.01.02.40.48; Tue, 01 Mar 2022 02:41:02 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=JCQyIrF8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234298AbiCAK3p (ORCPT + 99 others); Tue, 1 Mar 2022 05:29:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234286AbiCAK3m (ORCPT ); Tue, 1 Mar 2022 05:29:42 -0500 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55EFC5E76E; Tue, 1 Mar 2022 02:28:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1646130538; x=1677666538; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Fvtor8IGLpEt4IVg3IxMVK83oP7Tsh9UR2yVHJEbIcE=; b=JCQyIrF831jjLpfvaSRTkXwnMzZr53PKGA97lXhanxfjvMkxH3SK2BrB pTyEAHjS2z/+CEfhx3b9z+G3jYXBqi1/8meWNo1lktQCroHFoHX2h3/lH 2gco4Gq/QUPRoylL+hV+v8NH4qGJfVEc519Tn6PISJ+qcT3Q9OxOQYnk0 s=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 01 Mar 2022 02:28:57 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2022 02:28:57 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Tue, 1 Mar 2022 02:28:57 -0800 Received: from c-sanm-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Tue, 1 Mar 2022 02:28:52 -0800 From: Sandeep Maheswaram To: Greg Kroah-Hartman , Felipe Balbi , Stephen Boyd , Doug Anderson , Matthias Kaehlcke , Mathias Nyman , Pawel Laszczak , Peter Chen , Roger Quadros , Aswath Govindraju CC: , , , , , Sandeep Maheswaram Subject: [PATCH v2 3/3] usb: dwc: host: add xhci_plat_priv quirk XHCI_SKIP_PHY_INIT Date: Tue, 1 Mar 2022 15:58:27 +0530 Message-ID: <1646130507-26796-4-git-send-email-quic_c_sanm@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1646130507-26796-1-git-send-email-quic_c_sanm@quicinc.com> References: <1646130507-26796-1-git-send-email-quic_c_sanm@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org dwc3 manages PHY by own DRD driver, so skip the management by HCD core. During runtime suspend phy was not getting suspend because runtime_usage value is 2. Signed-off-by: Sandeep Maheswaram --- drivers/usb/dwc3/host.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c index eda8719..d4fcf06 100644 --- a/drivers/usb/dwc3/host.c +++ b/drivers/usb/dwc3/host.c @@ -13,6 +13,12 @@ #include #include "core.h" +#include +#include + +static const struct xhci_plat_priv xhci_plat_dwc3_xhci = { + .quirks = XHCI_SKIP_PHY_INIT, +}; static void dwc3_host_fill_xhci_irq_res(struct dwc3 *dwc, int irq, char *name) @@ -122,6 +128,13 @@ int dwc3_host_init(struct dwc3 *dwc) } } + ret = platform_device_add_data(xhci, &xhci_plat_dwc3_xhci, + sizeof(xhci_plat_dwc3_xhci)); + if (ret) { + dev_err(dwc->dev, "failed to add data to xHCI\n"); + goto err; + } + ret = platform_device_add(xhci); if (ret) { dev_err(dwc->dev, "failed to register xHCI device\n"); -- 2.7.4