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From:   "Wu, Hao" <hao.wu@intel.com>
To:     "Zhang, Tianfei" <tianfei.zhang@intel.com>,
        "trix@redhat.com" <trix@redhat.com>,
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Subject: RE: [PATCH v3 2/5] fpga: dfl: add features in dfl_fpga_cdev
Thread-Topic: [PATCH v3 2/5] fpga: dfl: add features in dfl_fpga_cdev
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Date:   Tue, 1 Mar 2022 06:59:34 +0000
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> -----Original Message-----
> From: Zhang, Tianfei <tianfei.zhang@intel.com>
> Sent: Tuesday, March 1, 2022 2:21 PM
> To: Wu, Hao <hao.wu@intel.com>; trix@redhat.com; mdf@kernel.org; Xu, Yilu=
n
> <yilun.xu@intel.com>; linux-fpga@vger.kernel.org; linux-doc@vger.kernel.o=
rg
> Cc: linux-kernel@vger.kernel.org; corbet@lwn.net; Zhang, Tianfei
> <tianfei.zhang@intel.com>
> Subject: [PATCH v3 2/5] fpga: dfl: add features in dfl_fpga_cdev
>=20
> Introducing features in dfl_fpga_cdev during DFL enumeration.

It's a little confusing, maybe flags is a better name.

> On OFS, we will add more extensions or features in DFL in
> future, so adding a new member "features"in dfl_fpga_cdev.
> For example, in the legacy model, the AFU was connected to
> Port device, but in "multiple VFs per PR slot" model, the
> AFU or PR slot without connected to Port device directly,
> so in this model, we only can access the resource of AFU
> or PR slot via VFs. In this patch, we introducing a new
> flags DFL_FEAT_PORT_CONNECTED_AFU to distinguish them.

Please consider where the flags should be, cdev is the container
of all DFLs, is it possible that one cdev contains two ports, one
has AFU, the other one doesn't?

Hao

>=20
> Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
> ---
>  drivers/fpga/dfl.c | 6 +++++-
>  drivers/fpga/dfl.h | 5 +++++
>  2 files changed, 10 insertions(+), 1 deletion(-)
>=20
> diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
> index 599bb21d86af..5872031c2e9f 100644
> --- a/drivers/fpga/dfl.c
> +++ b/drivers/fpga/dfl.c
> @@ -1124,6 +1124,7 @@ static void build_info_complete(struct
> build_feature_devs_info *binfo)
>  static int parse_feature_fiu(struct build_feature_devs_info *binfo,
>  			     resource_size_t ofst)
>  {
> +	struct dfl_fpga_cdev *cdev =3D binfo->cdev;
>  	int ret =3D 0;
>  	u32 offset;
>  	u16 id;
> @@ -1160,8 +1161,11 @@ static int parse_feature_fiu(struct
> build_feature_devs_info *binfo,
>  	v =3D readq(binfo->ioaddr + NEXT_AFU);
>=20
>  	offset =3D FIELD_GET(NEXT_AFU_NEXT_DFH_OFST, v);
> -	if (offset)
> +	if (offset) {
> +		if (dfh_id_to_type(id) =3D=3D PORT_ID)
> +			cdev->features |=3D DFL_FEAT_PORT_CONNECTED_AFU;
>  		return parse_feature_afu(binfo, offset);
> +	}
>=20
>  	dev_dbg(binfo->dev, "No AFUs detected on FIU %d\n", id);
>=20
> diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
> index 1fd493e82dd8..6171bcdcb3c5 100644
> --- a/drivers/fpga/dfl.h
> +++ b/drivers/fpga/dfl.h
> @@ -461,6 +461,9 @@ int dfl_fpga_enum_info_add_irq(struct
> dfl_fpga_enum_info *info,
>  			       unsigned int nr_irqs, int *irq_table);
>  void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);
>=20
> +/* in legacy model, the AFU was connected to Port device */
> +#define DFL_FEAT_PORT_CONNECTED_AFU  BIT_ULL(0)
> +
>  /**
>   * struct dfl_fpga_cdev - container device of DFL based FPGA
>   *
> @@ -470,6 +473,7 @@ void dfl_fpga_enum_info_free(struct
> dfl_fpga_enum_info *info);
>   * @lock: mutex lock to protect the port device list.
>   * @port_dev_list: list of all port feature devices under this container=
 device.
>   * @released_port_num: released port number under this container device.
> + * @features: features discovered during DFL enumeration.
>   */
>  struct dfl_fpga_cdev {
>  	struct device *parent;
> @@ -478,6 +482,7 @@ struct dfl_fpga_cdev {
>  	struct mutex lock;
>  	struct list_head port_dev_list;
>  	int released_port_num;
> +	u64 features;
>  };
>=20
>  struct dfl_fpga_cdev *
> --
> 2.26.2