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From:   Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com>
To:     adrian.hunter@intel.com, ulf.hansson@linaro.org, robh+dt@kernel.org
Cc:     quic_asutoshd@quicinc.com, quic_rampraka@quicinc.com,
        quic_pragalla@quicinc.com, quic_sartgarg@quicinc.com,
        quic_nitirawa@quicinc.com, quic_sayalil@quicinc.com,
        agross@kernel.org, bjorn.andersson@linaro.org,
        krzysztof.kozlowski@canonical.com, linux-arm-msm@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com>
Subject: [PATCH V1] arm64: dts: qcom: sc7280: Add GCC hardware register dt entry
Date:   Tue,  1 Mar 2022 16:42:03 +0530
Message-Id: <1646133123-22256-1-git-send-email-quic_c_sbhanu@quicinc.com>
Precedence: bulk

Add GCC hardware register dt entry for eMMC and SD card.

Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index c07765d..2b8461d 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -881,6 +881,9 @@
 			mmc-hs400-1_8v;
 			mmc-hs400-enhanced-strobe;
 
+			/* Add dt entry for gcc hw reset */
+			resets = <&gcc GCC_SDCC1_BCR>;
+			reset-names = "core_reset";
 			sdhc1_opp_table: opp-table {
 				compatible = "operating-points-v2";
 
@@ -2686,6 +2689,9 @@
 
 			qcom,dll-config = <0x0007642c>;
 
+			/* Add dt entry for gcc hw reset */
+			resets = <&gcc GCC_SDCC2_BCR>;
+			reset-names = "core_reset";
 			sdhc2_opp_table: opp-table {
 				compatible = "operating-points-v2";
 
-- 
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