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To:     Matthias Brugger <matthias.bgg@gmail.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>, kernel@collabora.com,
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        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-mediatek@lists.infradead.org
Subject: [PATCH v2 1/2] arm: dts: mediatek: Format mediatek,larbs as an array of phandles
Date:   Tue,  1 Mar 2022 15:31:46 -0500
Message-Id: <20220301203147.1143782-1-nfraprado@collabora.com>
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Commit 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas")
updated the mediatek,larbs property in the mediatek,iommu.yaml
dt-binding to make it clearer that the phandles passed to the property
are independent, rather than subsequent arguments to the first phandle.

Update the mediatek,larbs property in the arm Devicetrees to use the
same formatting. This change doesn't impact any behavior: the compiled
dtb is exactly the same. It does however fix the warnings generated by
dtbs_check.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

---
v1: https://lore.kernel.org/linux-mediatek/20220225225315.80220-1-nfraprado@collabora.com/

Changes in v2:
- Split arm and arm64 changes into separate commits

 arch/arm/boot/dts/mt2701.dtsi  | 2 +-
 arch/arm/boot/dts/mt7623n.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 4776f85d6d5b..64722285228c 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -222,7 +222,7 @@ iommu: mmsys_iommu@10205000 {
 		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&infracfg CLK_INFRA_M4U>;
 		clock-names = "bclk";
-		mediatek,larbs = <&larb0 &larb1 &larb2>;
+		mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
 		#iommu-cells = <1>;
 	};
 
diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mt7623n.dtsi
index bcb0846e29fd..f9e031621c80 100644
--- a/arch/arm/boot/dts/mt7623n.dtsi
+++ b/arch/arm/boot/dts/mt7623n.dtsi
@@ -107,7 +107,7 @@ iommu: mmsys_iommu@10205000 {
 		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&infracfg CLK_INFRA_M4U>;
 		clock-names = "bclk";
-		mediatek,larbs = <&larb0 &larb1 &larb2>;
+		mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
 		#iommu-cells = <1>;
 	};
 
-- 
2.35.1