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[2620:137:e000::1:20]) by mx.google.com with ESMTP id d22-20020a170906641600b006d6e3ce8211si4060133ejm.779.2022.03.02.10.35.01; Wed, 02 Mar 2022 10:35:24 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="c3/uB/Vn"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243341AbiCBO6s (ORCPT + 99 others); Wed, 2 Mar 2022 09:58:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243315AbiCBO6h (ORCPT ); Wed, 2 Mar 2022 09:58:37 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E1FE32057; Wed, 2 Mar 2022 06:57:51 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7CDA061689; Wed, 2 Mar 2022 14:57:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B2AA4C004E1; Wed, 2 Mar 2022 14:57:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1646233070; bh=vzWBAbR4Oux6P/RO30qmN2wLxTgTR+gOm30Ed6V+lZE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c3/uB/VnUxQZ0nugmcUrJAOl/xhNVT8YlvEG1d37kvBHmvgxv7TAAPNs8GyE1hs5g hvuAkGWExn9+Sdk88L5P9SBnOxPgE73CIx0DD9S1S465gKaa/B3byLcGzCDx4bbywa 7EVWVR0/Bc2XvHbx9Rr2KYtFa9qqzJrtcH1m0awFl3RcgPSiRrGbVg6AwB7e3mz0XN is/0YdRI8zv0wj+zSv52yRdgYoZ7DxnFmJnXdTd2+JRy9vAKXqyy5HH5ChUzppIHkh idAahAj/ijAD5gOXiuf18pdutHzzkRgyBYqESUiYCLB+zSSI3XQKCKgkASOjA3Cpuw 8VJ8Ye/6QNsFQ== Received: by pali.im (Postfix) id 0792C95D; Wed, 2 Mar 2022 15:57:48 +0100 (CET) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Lorenzo Pieralisi , Bjorn Helgaas , Rob Herring , Andrew Lunn , Thomas Petazzoni , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Russell King Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/4] PCI: Add PCI_EXP_SLTCTL_ASPL_DISABLE macro Date: Wed, 2 Mar 2022 15:57:30 +0100 Message-Id: <20220302145733.12606-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220302145733.12606-1-pali@kernel.org> References: <20220302145733.12606-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add macro defining Auto Slot Power Limit Disable bit in Slot Control Register. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Acked-by: Bjorn Helgaas --- include/uapi/linux/pci_regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index bee1a9ed6e66..108f8523fa04 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -616,6 +616,7 @@ #define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */ #define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */ #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */ +#define PCI_EXP_SLTCTL_ASPL_DISABLE 0x2000 /* Auto Slot Power Limit Disable */ #define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000 /* In-band PD disable */ #define PCI_EXP_SLTSTA 0x1a /* Slot Status */ #define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */ -- 2.20.1