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[2620:137:e000::1:18]) by mx.google.com with ESMTPS id n3-20020a17090aab8300b001bc7a6e6255si458058pjq.12.2022.03.02.16.32.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 16:32:59 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) client-ip=2620:137:e000::1:18; Authentication-Results: mx.google.com; dkim=pass header.i=@jms.id.au header.s=google header.b=RKeNmy3F; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 5587D2335EA; Wed, 2 Mar 2022 15:42:51 -0800 (PST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229565AbiCBWeB (ORCPT + 99 others); Wed, 2 Mar 2022 17:34:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229453AbiCBWd6 (ORCPT ); Wed, 2 Mar 2022 17:33:58 -0500 Received: from mail-qk1-x72f.google.com (mail-qk1-x72f.google.com [IPv6:2607:f8b0:4864:20::72f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FE0D4F45C; Wed, 2 Mar 2022 14:33:14 -0800 (PST) Received: by mail-qk1-x72f.google.com with SMTP id v5so2580012qkj.4; Wed, 02 Mar 2022 14:33:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jms.id.au; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=MH2CJfGKAeTvDpXrtXLMMm+AC8F6kORH3TEKSbCrNfI=; b=RKeNmy3FgK0W71enFNR21BoAMLPgQXHsfgsQCPyNwyuvfc7MZfNodSByaq0Xp2JeOP tf5cFIpBZ6//AkroEjrR/w9M87A3MtinzkU6NksETqZj3V63/skTEg0IrWKa/DdihjUM A2ac1oIm9AhN8QgbHXUX9hs/Ta4d9tz0s/WAU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=MH2CJfGKAeTvDpXrtXLMMm+AC8F6kORH3TEKSbCrNfI=; b=6mRQY/espVYJBbUDhVgXKRV1zrJrY+9xTWwL9RnmFCjuO9sgFgkXPe/ZcGurydP1/G y+/exoCl7hjZefbDupHayEiTZYjdMwdUlZTYHqyMBl1OCRLTxL441qyGCXzlIEOOHEV0 08gtVQQnRWcOhj94CPqB4dflVGDcIkwyGrDb0MwOmLNbqd3I43hvTlg1rykxLdXvBfTw 92Gmq/Yf+lxgbfjQHOeimAoIWATZmTP4ncm2ZGWZYcSwwVIv6GhRuYFi+GiculV2bN3J SNiTbeu6cDGJJxSqtdMC0CphhzrAILi1qeyF4/hzD0qMsr9mS1W+Ar9LZDvRSQyhbcwh TePA== X-Gm-Message-State: AOAM5317+yejw+FLV2d5KK/VK3YFyUUapSa38PYE62MJurm1WHUUiuHP 5LY+eZ/uK8oCahKPB4KD9E12vbNAwLv9Y6yietM= X-Received: by 2002:a37:f903:0:b0:648:ca74:b7dc with SMTP id l3-20020a37f903000000b00648ca74b7dcmr17319869qkj.666.1646260393417; Wed, 02 Mar 2022 14:33:13 -0800 (PST) MIME-Version: 1.0 References: <20220302173114.927476-1-clg@kaod.org> <20220302173114.927476-9-clg@kaod.org> In-Reply-To: <20220302173114.927476-9-clg@kaod.org> From: Joel Stanley Date: Wed, 2 Mar 2022 22:33:00 +0000 Message-ID: Subject: Re: [PATCH v2 08/10] spi: aspeed: Add support for the AST2400 SPI controller To: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Cc: linux-spi@vger.kernel.org, linux-mtd , Mark Brown , Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-aspeed , Andrew Jeffery , Chin-Ting Kuo , devicetree , Rob Herring , Linux ARM , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2 Mar 2022 at 17:31, C=C3=A9dric Le Goater wrote: > > Extend the driver for the AST2400 SPI Flash Controller (SPI). This > controller has a slightly different interface which requires > adaptation of the 4B handling. Summary of features : > > . host Firmware > . 1 chip select pin (CE0) > . slightly different register set, between AST2500 and the legacy > controller > . no segment registers > . single, dual mode. > > Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley > --- > drivers/spi/spi-aspeed-smc.c | 33 ++++++++++++++++++++++++++++++++- > 1 file changed, 32 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c > index e133984d3c95..8c6d7f79d97f 100644 > --- a/drivers/spi/spi-aspeed-smc.c > +++ b/drivers/spi/spi-aspeed-smc.c > @@ -32,6 +32,7 @@ > #define CTRL_IO_DUAL_DATA BIT(29) > #define CTRL_IO_QUAD_DATA BIT(30) > #define CTRL_COMMAND_SHIFT 16 > +#define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */ > #define CTRL_IO_DUMMY_SET(dummy) \ > (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6)) > #define CTRL_CE_STOP_ACTIVE BIT(2) > @@ -272,6 +273,8 @@ static bool aspeed_spi_supports_op(struct spi_mem *me= m, const struct spi_mem_op > return spi_mem_default_supports_op(mem, op); > } > > +static const struct aspeed_spi_data ast2400_spi_data; > + > static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_m= em_op *op) > { > struct aspeed_spi *aspi =3D spi_controller_get_devdata(mem->spi->= master); > @@ -301,6 +304,9 @@ static int do_aspeed_spi_exec_op(struct spi_mem *mem,= const struct spi_mem_op *o > addr_mode |=3D (0x11 << chip->cs); > else > addr_mode &=3D ~(0x11 << chip->cs); > + > + if (op->addr.nbytes =3D=3D 4 && chip->aspi->data =3D=3D &= ast2400_spi_data) > + ctl_val |=3D CTRL_IO_ADDRESS_4B; > } > > if (op->dummy.buswidth && op->dummy.nbytes) > @@ -392,7 +398,13 @@ static int aspeed_spi_chip_set_default_window(struct= aspeed_spi_chip *chip) > struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] =3D { 0 }= ; > struct aspeed_spi_window *win =3D &windows[chip->cs]; > > - aspeed_spi_get_windows(aspi, windows); > + /* No segment registers for the AST2400 SPI controller */ > + if (aspi->data =3D=3D &ast2400_spi_data) { > + win->offset =3D 0; > + win->size =3D aspi->ahb_window_size; > + } else { > + aspeed_spi_get_windows(aspi, windows); > + } > > chip->ahb_base =3D aspi->ahb_base + win->offset; > chip->ahb_window_size =3D win->size; > @@ -455,6 +467,10 @@ static int aspeed_spi_chip_adjust_window(struct aspe= ed_spi_chip *chip, > struct aspeed_spi_window *win =3D &windows[chip->cs]; > int ret; > > + /* No segment registers for the AST2400 SPI controller */ > + if (aspi->data =3D=3D &ast2400_spi_data) > + return 0; > + > /* > * Due to an HW issue on the AST2500 SPI controller, the CE0 > * window size should be smaller than the maximum 128MB. > @@ -539,6 +555,12 @@ static int aspeed_spi_dirmap_create(struct spi_mem_d= irmap_desc *desc) > else > addr_mode &=3D ~(0x11 << chip->cs); > writel(addr_mode, aspi->regs + CE_CTRL_REG); > + > + /* AST2400 SPI controller sets 4BYTE address mode in > + * CE0 Control Register > + */ > + if (op->addr.nbytes =3D=3D 4 && chip->aspi->data =3D=3D &= ast2400_spi_data) > + ctl_val |=3D CTRL_IO_ADDRESS_4B; > } > > /* READ mode is the controller default setting */ > @@ -805,6 +827,14 @@ static const struct aspeed_spi_data ast2400_fmc_data= =3D { > .segment_reg =3D aspeed_spi_segment_reg, > }; > > +static const struct aspeed_spi_data ast2400_spi_data =3D { > + .max_cs =3D 1, > + .hastype =3D false, > + .we0 =3D 0, > + .ctl0 =3D 0x04, > + /* No segment registers */ > +}; > + > static const struct aspeed_spi_data ast2500_fmc_data =3D { > .max_cs =3D 3, > .hastype =3D true, > @@ -849,6 +879,7 @@ static const struct aspeed_spi_data ast2600_spi_data = =3D { > > static const struct of_device_id aspeed_spi_matches[] =3D { > { .compatible =3D "aspeed,ast2400-fmc", .data =3D &ast2400_fmc_da= ta }, > + { .compatible =3D "aspeed,ast2400-spi", .data =3D &ast2400_spi_da= ta }, > { .compatible =3D "aspeed,ast2500-fmc", .data =3D &ast2500_fmc_da= ta }, > { .compatible =3D "aspeed,ast2500-spi", .data =3D &ast2500_spi_da= ta }, > { .compatible =3D "aspeed,ast2600-fmc", .data =3D &ast2600_fmc_da= ta }, > -- > 2.34.1 >