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[2620:137:e000::1:20]) by mx.google.com with ESMTP id 18-20020a170906101200b006ceafb3c992si2075392ejm.391.2022.03.03.15.11.48; Thu, 03 Mar 2022 15:12:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=o2c+ye5B; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231135AbiCCTH3 (ORCPT + 99 others); Thu, 3 Mar 2022 14:07:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229536AbiCCTH2 (ORCPT ); Thu, 3 Mar 2022 14:07:28 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D5C419D751; Thu, 3 Mar 2022 11:06:42 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D097F61A8A; Thu, 3 Mar 2022 19:06:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 41F4FC340F3; Thu, 3 Mar 2022 19:06:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1646334401; bh=2BtpIBsXVCJxVQ/oh3K2FgXEMXiekUDLQX9xD2gdbLM=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=o2c+ye5BqYrayS6wcIkhykEd9oMUM08fnMBunZ6ubqX+UPCADV0E3K1UilobnxEPQ sjmgxT04DSYUChMdCZVaAVyy6CXFMzPmUDVfXCOHmMz1U7anuFgSLwFqFWWlO6vpm/ Ibuza1+FbskVwliS18eABoFLCDlTEAmnkV7CiQX7bG0YpjPE8COYneNTvKag0LoL5G c4OqdEIfpQaaAiypnu9/cZpft0YHLK88txfnlhsoopUuEcX1UIDkDqZgGS03IL5Mn1 zqj05azs8MVzTuDztpZrpkyYk5qi0sb4Td1zcAw+k3CjFcSFYw7+6ijKAIPw82Etxz DW+fCwyHjboxg== Received: by mail-ed1-f43.google.com with SMTP id q17so7878712edd.4; Thu, 03 Mar 2022 11:06:41 -0800 (PST) X-Gm-Message-State: AOAM533+fFcS5jz4NiB3e3Sv6PMbcD1sMv/j2t9RTsYMeiOcyVRjKUSS ukmku3Z0jTr2+zzBJZAWmeQc/vwG3WH+gRVCdQ== X-Received: by 2002:a05:6402:4384:b0:413:9e36:b56f with SMTP id o4-20020a056402438400b004139e36b56fmr25115772edc.280.1646334399480; Thu, 03 Mar 2022 11:06:39 -0800 (PST) MIME-Version: 1.0 References: <20220215081334.788419-1-peng.fan@oss.nxp.com> In-Reply-To: From: Rob Herring Date: Thu, 3 Mar 2022 13:06:27 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] dt-bindings: serial: fsl-lpuart: Add imx93 compatible string To: Peng Fan Cc: "Peng Fan (OSS)" , "gregkh@linuxfoundation.org" , "linux-serial@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Feb 27, 2022 at 6:44 PM Peng Fan wrote: > > Hi Rob, > > > Subject: Re: [PATCH] dt-bindings: serial: fsl-lpuart: Add imx93 compatible > > string > > > > On Tue, Feb 15, 2022 at 04:13:34PM +0800, Peng Fan (OSS) wrote: > > > From: Peng Fan > > > > > > The lpuart on i.MX93 is derived from i.MX8ULP with some industrial > > > enhancements, it uses three compatible strings, so update the > > > > Looks like it's 2 compatible strings... > > Oh, yes. i.MX8ULP/7ULP is same uart IP. > > > > > > compatible string for i.MX93. But for a few instants, > > > > s/instants/instances/ > > > > > DTR_B, DSR_B, DCD_B and RIN_B pins are supported, so use one > > > compatible string fsl,imx93-lpuart-v2 > > > > If the differences are just what gets pinned out, then I think the differences > > should be handled with separate properties. We probably already have some. > > > > Plus, while you may have all the above signals, a board design may still only > > use a subset. > > It is SoC integration level with above features not support in some instances, > so no such signals connected to SoC pin. > > Saying LPUART IP itself support DTR/DSR/DCD/RIN, but instance A has the > feature disabled when doing SoC integration, instance B has the feature enabled > when doing SoC integration. What's your suggestion with such case? Unless it changes the register interface in a non-compatible way that the driver needs to know about, I would not do a different compatible. For example, register offsets change. Rob